猎头推荐上海高薪（年薪30w以上）RFIC设计职位

jiyou

猎头推荐上海高薪（年薪30w以上）RFIC设计职位

JD：
RF/Analog IC Design:
You will work closely with a world-class team of IC designers to design
high-performance ICs with RF, analog, mixed-signal, and digital systems
integrated on a single chip. Responsible for design and verification of
RF and mixed-signal circuits. Characterize and debug relevant blocks.
Analyze the effects of non-idealities on circuit performance.
Work with system engineers in optimizing circuit designs and system
specification trade-offs. Report the results of IC design, analysis
and evaluation. This position requires strong communication skills
and the ability to work closely with a team of IC design and layout
designers. We are looking for people with versatility, initiative
and the ability to adapt to a dynamic startup environment.
JD：
RF/Analog IC Layout:
You will work closely with a world-class team of IC designers to
perform physical layout of high-performance ICs with RF, analog,
mixed-signal, and digital systems integrated on a single chip.
Responsibilities include block-level layout and verification,
and top level routing. We are looking for people with versatility,
initiative and the ability to adapt to a dynamic startup environment.
JD:
IC Test:
You will be responsible for testing and characterization of
RF/analog/mixed-signal ICs. You will work closely with RF
systems engineers and RF/Analog IC designers to fully evaluate
the performance of MaxLinear抯 products. You will learn to design
and debug RF PCB boards. You will receive training on using and
automating various test equipments. You will be expected to master
test automation programming languages LabView and VBA .
You will participate in correlation work between lab test and
production test. Will generate all chip validation support documents
and will organize test data for referencing.  Should have excellent
written and verbal communications skills. We are looking for people
with versatility, initiative and the ability to adapt to a dynamic
startup environment.


JD:
This is a physical layer systems engineering position which involves
analyzing multiple algorithms for a given problem, selecting one based
on some optimization/ implementation criteria, doing simulations to
validate performance / complexity tradeoffs, fixed point implementations
and specification for ASIC group, working with the ASIC group through
implementation phase by providing test vectors and so on.
Also, the position involves validating the solutions in the lab
(FPGA platform + ASIC), so hands-on experience with testing is valuable.  
  
You should have a strong background in the following:
?        Deep knowledge of random processes
?        Estimation and detection theory
?        Digital communications, digital signal processing
?        Wireless channels, channel equalization techniques
?        Various physical layer implementations such as OFDM modem design.


You should have significant experience in overall modem design, and be
interested in product development (as opposed to pure research). This
involves understanding the front end blocks (such as AGC, digital filters),
the demodulator blocks (channel estimation, synchronization etc.) and
FEC blocks and the overall context in which they work together.
Experience in designing one or more of these is necessary, and should
include experience with analyzing and picking algorithms, tradeoff of
fixed point issues, for example.

Knowledge of various multiple access techniques is desired.
OFDM modem design experience is a major plus.

High energy and integrity are a must. We are looking for people who
will thrive in a high energy and dynamic startup environment, and who
have leadership potential.


MSEE + 5 or Ph.D (EE) + 3 desired.
The bar is high so candidates are expected to self select.


please send resume to yuxin.huang@ji-you.cn
or contact msn:yuxin.huang@live.cn

[

rousong

[em07]

lxhua

strong 强强强

stevenzz100

可惜是在上海

yantaisgj

ls高手?
30以上万年薪可以不管地域了吧?

stevenzz100

主要是在北京住习惯了

oyggj

牛人啊.呵呵