以抗流線圈抑制非遮蔽雙絞線之共模雜訊

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【文件名】:07127@52RD_以抗流線圈抑制非遮蔽雙絞線之共模雜訊.pdf
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Index
中文摘要………………………………………………………………………………. i
Abstract………………………………………………………………………………… ii
誌謝…………………………………………………………………………………….. iii
Index…………………………………………………………………………………… iv
List of Tables…………………………………………………………………………... vi
List of Figures………………………………………………………………………….. vii
Chapter1 Introduction…………………………………………………………………… 1
1.1 LAN technologies and UTP cabling…………………………………………… 1
1.2 Why noise reduction on the UTP cable is important…………………………… 1
Chapter2 Theory and Analysis Method…………………………………………………. 3
2.1 Differential-to-common-mode conversion on an UTP cable………………….. 3
2.2 Differential-Mode versus Common-Mode Current…………………………… 5
2.3 Common-mode choke…………………………………………………………. 7
2.3.1 Role of the common-mode choke…………………………………………. 7
2.3.2 Structure and mechnisms………………………………………………….. 8
2.3.3 Material and the location………………………………………………… 10
2.3.4 Model……………………………………………………………………. 13
2.3.5 Further derivation of the transmission parameters………………………. 14
2.4 Transmission matrix of a perfectly balanced pair cable…………..…………... 15
2.5 Transmission matrix of the unbalanced elements……………………………... 17
2.6 Transmission matrix of the completed system………………………………… 17
2.7 Longitudinal conversion transfer loss…………………………………………. 19
2.8 Differential-mode current emission model……………………………………. 19
2.9 Common-mode current emission model………………………………………. 23
Chapter3 Simulation and Experiment…………………………………………………. 24
3.1 RLGC equations of category-5 cable…………………………………………… 24
3.2 Transmission matrix of the unbalanced elements for the simulation…………… 29
3.3 Transmission matrix of the common-mode choke for the simulation………….. 29
3.4 Longitudinal Conversion Transfer Loss Simulation……………………………. 33
3.4.1 Cable length 100m……………………………………………………….. 33
3.4.1.1 CMC location variation along the 100m cable…………………... 33
3.4.1.2 Unbalanced capacitor location variation along the 100m cable…. 35
3.4.1.3 Unbalanced capacitor variations…………………………………. 36
3.4.1.4 Two unbalanced capacitors C13 and C23………………………… 37
3.4.1.5 Series unbalanced resistor R11…………………………………… 38
3.4.1.6 Shunt unbalanced resistor R13…………………………………… 39
3.4.2 Effects of the different winding inductance……………………………... 40
3.4.3 Cable length 4m…………………………………………………………. 42
3.5 Measurement of the Radiated Emissions………………………………………. 43
v
3.6 Pspice simulation for verification on the proposed models……………………. 49
Chapter4 Conclusion and future work………………………………………………… 52
4.1 Conclusions…………………………………………………………………….. 52
4.2 Future work…………………………………………………………………….. 52
References……………………………………………………………………………… 53
Appendix A…………………………………………………………………………….. 54
簡歷…………………………………………………………………………………… 60
vi
List of Tables
Table1 Parameters for CMC simulation……………………………………………….. 30
Table2 CMC locations…………………………………………………………………. 33
Table3 Unbalanced capacitor locations………………………………………………… 35
Table4 Unbalanced capacitor variations………………………………………………. 36
Table5 Two unbalanced capacitors C13 and C23………………………………………. 37
Table6 Unbalanced resistor variations………………………………………………… 38
Table7 Shunt-unbalanced resistor variations………………………………………….. 39
Table8 LCTL ratio @100MHz @ 4 meter cable length………………………………. 43
Table9 (a) Set-up parameters for the measurement of the radiated emission at input clock 20MHz 43
Table9 (b) Set-up parameters for the measurement of the radiated emission at input clock 100MHz
……………………………………………………………………………………. 44
Table10 (a) Radiated emission measurement results at input clock 20MHz
–unbalance capacitors versus horizontal emission……………………………… 44
Table10 (b) Radiated emission measurement results at input clock 20MHz
–unbalance capacitors versus vertical emission………………………………… 45
Table10 (c) Radiated emission measurement results at input clock 100MHz
–100pF unbalance capacitor versus vertical emission…………………………… 45
Table10 (d) Radiated emission measurement results at input clock 100MHz
–100pF unbalance capacitor versus horizontal emission………………………… 45
Table10 (e) Radiated emission measurement results at input clock 100MHz
– unbalance capacitors versus vertical emission…………………………………. 46
Table10 (f) Radiated emission measurement results at input clock 100MHz
– unbalance capacitors versus horizontal emission………………………………. 46
Table11 Pspice set-up parameters……………………………………………………….. 49
vii
List of Figures
Fig1 An unbalanced circuit element within the transmitter causes current circulate through the
external cabling and product chassis………………………………………………… 5
Fig2 Decomposition of the total currents…………………………………………………. 5
Fig.3 Radiated emissions of differential-mode currents…………………………………... 7
Fig.4 Radiated emissions of common-mode currents……………………………………… 7
Fig.5 Effect of a common-mode choke on the currents of a two wire…………………….. 8
Fig.6 Effect of a common-mode choke on the differential-mode components……………. 9
Fig.7 Effect of a common-mode choke on the common-mode components……………… 9
Fig.8 A simple way of winding a common-mode choke………………………………….. 9
Fig.9 Parasitic capacitance………………………………………………………………… 10
Fig.10 Frequency response of the relative permeabilities of MnZn and NiZn…………… 11
Fig.11 Measured impedance of inductors formed by winding five turns of #28 gauge wire on
MnZn cores………………………………………………………………………... 12
Fig.12 Measured impedance of inductors formed by winding five turns of #28 gauge wire on
NiZn cores…………………………………………………………………………. 13
Fig.13 A common-mode choke……………………………………………………………. 13
Fig.14 Rotated CMC………………………………………………………………………. 14
Fig.15 CMC represented as two-port network……………………………………………. 14
Fig.16 CMC represented as four-port network…………………………………………… 14
Fig.17 Three conductor lines……………………………………………………………… 15
Fig.18 Matrix representation of perfectly balance pair cable……………………………... 16
Fig.19 Model of balance pair cable……………………………………………………….. 17
Fig.20 Matrix representation of balanced pair cable circuit……………………………… 18
Fig.21 Computation of the far-field radiated emissions of a two-conductor line as the
superposition of the fields due to each conductor………………………………… 19
Fig.22 A simplified estimate of the maximum radiated emissions due to differential-mode
currents with constant distribution………………………………………………. 22
Fig.23 (a) Differential-mode scatting parameters S11 S12 for UTP………………………. 25
Fig.23 (b) Differential-mode scatting parameters S21 S22 for UTP………………………. 25
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Fig.24 (a) Common-mode scatting parameters S11 S12 for UTP…………………………. 26
Fig.24 (b) Common-mode scatting parameters S21 S22 for UTP…………………………. 26
Fig.25 Loop resistance Rn, Rc…………………………………………………………… 27
Fig.26 Line inductance Ln, Lc…………………………………………………………… 27
Fig.27 Shunt conductance Gn, Gc……………………………………………………….. 28
Fig.28 Shunt capacitance Cn,Cc…………………………………………………………. 28
Fig.29 A CMC equivalent circuit………………………………………………………… 30
Fig.30 (a) Input impedance of CMC – magnitude of winding inductance 24 uH………… 30
Fig.30 (b) Input impedance of CMC – phase of winding inductance 24 uH…………….. 31
Fig.30 (c) Input impedance of CMC – magnitude of winding inductance 47 uH………... 31
Fig.30 (d) Input impedance of CMC – phase of winding inductance 47 uH……………. 31
Fig.30 (e) Input impedance of CMC – magnitude of winding inductance 140 uH……… 32
Fig.30 (f) Input impedance of CMC – phase of winding inductance 140 uH…………… 32
Fig.31 Model of balanced pair lines with partial unbalance and CMC………………….. 33
Fig.32 Variation of CMC location……………………………………………………….. 34
Fig.33 Fixed C13 = 100pF………………………………………………………………. 34
Fig.34 Variation of unbalanced capacitor locations…………………………………….. 35
Fig.35 Variation of unbalanced capacitor locations –NO CMC………………………... 36
Fig.36 Unbalanced capacitor variations………………………………………………… 37
Fig.37 Two unbalanced capacitors C13 and C23……………………………………….. 38
Fig.38 Series unbalanced resistor R11………………………………………………….. 39
Fig.39 Shunt-unbalanced resistor R13………………………………………………….. 40
Fig.40 Winding inductance Lp = Ls = 24 uH…………………………………………… 40
Fig.41 Winding inductance Lp = Ls = 47 uH…………………………………………… 41
Fig.42 Winding inductance Lp = Ls = 140 uH………………………………………….. 41
Fig.43 A comparison among three winding inductance………………………………… 41
Fig.44 Unbalanced capacitor variations without CMC (cable length 4m)……………… 42
Fig.45 Unbalanced capacitor variations with CMC (cable length 4m)………………….. 42
Fig.46 The radiated emission measurement system…………………………………….. 44
ix
Fig.47 Antenna to EUT…………………………………………………………………. 47
Fig.48 Right side of the cable…………………………………………………………… 47
Fig.49 Left side of the cable…………………………………………………………….. 48
Fig.50 ADVANTEST R3162 Spectrum Analyser and 8447F OPT H64 Amplifier……. 48
Fig.51 (a) Pspice circuits and inputs/outputs – 4 meter cable at input clock 100MHz….. 49
Fig.51 (b) Pspice circuits and inputs/outputs –100MHz differential input waveform…… 49
Fig.51 (c) Pspice circuits and inputs/outputs – output waveform measured at R31 and
R32……………………………………………………………………………. 50
Fig.51 (d) Pspice circuits and inputs/outputs – 4 meter cable with choke and unbalanced
capacitor at input clock 100MHz………………………………..…………… 50
Fig.51 (e) Pspice circuits and inputs/outputs – input waveform V1 minus V2………. 50
Fig.51 (f) Pspice circuits and inputs/outputs - output differential waveform measured
at R31 and R32……………………………………………………………… 51

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