【文件名】:06115@52RD_Behavioral modeling in VHDL simulation.pdf
【格 式】:pdf
【大 小】:175K
【简 介】:
USING AN EFFECTIVE TESTBENCH IS AN IMPORTANT PART
OF PROGRAMMABLE-LOGIC SIMULATION. KNOWING
WHICH VHDL FEATURES SUPPORT HIGH-LEVEL MODELING
HELPS REDUCE YOUR TESTBENCH-DEVELOPMENT TIME.
The effective use of simulation offers several advantages for product-development teams.
【目 录】:
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发表于 2006-1-15 15:35:00
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