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【文件名】:071127@52RD_hardware_design_verification.part1.rar
【格 式】:rar
【大 小】:3457K
【简 介】:
【目 录】:
I am pleased to introduce the Verification Methodology Manual for SystemVerilog, a book that will revolutionize the practices of verification engineers much as the RMM led designers to a better methodology with more predictable results. It encompasses all the latest techniques, including constrained-random stimulus generation, coverage-
driven verification, assertion-based verification, formal analysis, and system-level verification in an open, well-defined methodology. It introduces and illustrates these techniques with examples from SystemVerilog, the industry standard linking RTL design, testbenches, assertions, and coverage together in a coherent and comprehensive
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