Writing Testbenches using SystemVerilog

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Writing Testbenches using SystemVerilog
【文件名】:071123@52RD_Writing Testbenches using SystemVerilog.pdf
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This book focuses on the functional verification of hardware
designs using SystemVerilog. I expect the reader to have at least a
basic knowledge of VHDL, Verilog, OpenVera or e. Ideally, you
should have experience in writing models and be familiar with running
a simulation using any of the available VHDL or Verilog simulators.
There will be no detailed description of language syntax or
grammar. It may be a good idea to have a copy of a languagefocused
textbook or the SystemVerilog Language Reference Manual
as a reference along with this book. I do not describe a synthesizable
subset, nor limit the implementation of the verification techniques
to using that subset. Verification is a complex task: The
power of the SystemVerilog language will be used to its fullest.

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