求助！pwm产生

xiaorao

module pwm(clock,keyin,pwm_out);
input clock;
input [1:0] keyin;
output pwm_out;
reg [20:0] count;
reg [9:0] pwm_count;
reg pwm_reg;
always @(posedge clock)
begin
  count=count+1;
  if (count[15:6] < pwm_count)
     pwm_reg=1;
  else pwm_reg=0;
end
  always @(posedge count[15])
  begin
  if (keyin[0] == 1'b0)
   begin
   pwm_count=pwm_count+1;
   end
   else if (keyin[1] == 1'b0)
   begin
   pwm_count=pwm_count-1;
   end
end
assign pwm_out=pwm_reg;
endmodule
有什么问题没有，看不出来，谢谢大虾指点

vfdff

现在哪里不对?问题没有描述清楚