(有图片和目录)CMOS PLL Synthesizers: Analysis and Design

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Contents
List of Acronyms and Symbols ix
Preface xv
1 Introduction
1.1 MOTIVATION
1.2 SUMMARY OF BOOK
1.3 BOOK ORGANIZATION
REFERENCES
1
1
2
4
5
2 Frequency Synthesizer for Wireless Applications
2.1 DEFINITION AND CHARACTERISTICS
2.2 PHASE NOISE AND TIMING JITTER
7
7
8
2.2.1 Phase noise and spurious tone 8
2.2.2 Timing jitter
2.3 IMPLEMENTATION OF FREQUENCY SYNTHESIZER
11
14
2.3.1 Direct analog frequency synthesizer 14
15
16
20
21
21
22
24
26
2.3.2 Direct digital frequency synthesizer
2.3.3 PLL-based frequency synthesizer
2.3.4 DLL-based frequency synthesizer
2.3.5 Hybrid frequency synthesizer
2.3.6 Summary and comparison of synthesizers
2.4 FREQUENCY SYNTHESIZER FOR WIRELESS TRANSCEIVERS
2.5 OTHER APPLICATIONS OF PLL AND FREQUENCY SYNTHESIZER
REFERENCES
vi CMOS PLL Synthesizers: Analysis and Design
3 PLL Frequency Synthesizer 31
31
31
34
44
56
58
58
60
60
60
62
62
65
3.1 PLL FREQUENCY SYNTHESIZER BASICS
3.1.1 Basic building blocks of charge-pump PLL
3.1.2 Continuous-time linear phase analysis
3.1.3 Locking time
3.1.4 Tracking and acquisition
3.2 FAST-LOCKING TECHNIQUES
3.2.1 Bandwidth gear-shifting
3.2.2 VCO pre-tuning
3.3 DISCRETE-TIME ANALYSIS AND NONLINEAR MODELING
3.3.1
3.3.2
z-domain transfer function and stability analysis
Nonlinear dynamic behavior modeling
3.4 DESIGN EXAMPLE: 2.4GHZ INTEGER-N PLL FOR BLUETOOTH
REFERENCES
4 Fractional-N PLL Synthesizer 69
69
70
73
73
73
74
87
90
90
91
92
95
98
4.1 FRACTIONAL-N FREQUENCY SYNTHESIZER
4.1.1 quantization noise to phase noise mapping
4.1.2 quantization noise to timing jitter mapping
4.2 A COMPARATIVE STUDY OF DIGITAL MODULATORS
4.2.1 Design considerations
4.2.2 Four types of digital modulators
4.2.3 Summary of comparative study
4.3 OTHER APPLICATIONS OF
4.3.1 Direct digital modulation
4.3.2 Frequency-to-digital conversion
4.4 MODELING AND SIMULATION OF
4.5 DESIGN EXAMPLE: 900MHz FOR GSM
REFERENCES
5 Enhanced Phase Switching Prescaler 103
103
103
105
107
107
108
110
110
111
112
113
115
5.1 PRESCALER ARCHITECTURE
5.1.1
5.1.2
5.1.3
5.1.4
Conventional prescaler
Phase switching prescaler
Injection-locked prescaler
Summary and comparison of prescalers
5.2
5.3
ENHANCED PHASE-SWITCHING PRESCALER
CIRCUIT DESIGN AND SIMULATION RESULTS
5.3.1
5.3.2
5.3.3
5.3.4
Eight 45°-spaced phases generation
8-to-1 multiplexer
Switching control circuit
Asynchronous frequency divider
5.4 DELAY BUDGET IN THE SWITCHING CONTROL LOOP
CMOS PLL Synthesizers: Analysis and Design vii
5.5 SPURS DUE TO NONIDEAL 45° PHASE SPACING
REFERENCES
117
123
6 Loop Filter With Capacitance Multiplier 127
127
127
128
131
133
137
138
141
141
142
145
148
149
6.1 LOOP FILTER ARCHITECTURE
6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
Passive loop filter
Dual-path loop filter
Sample-reset loop filter
Other loop filter architectures
Summary and comparison of loop filters
6.2
6.3
LOOP FILTER AND CHARGE-PUMP NOISE MAPPING
LOOP FILTER WITH CAPACITANCE MULTIPLIER
6.3.1
6.3.2
6.3.3
6.3.4
Third-order passive loop filter
Capacitance multiplier
Simulation of loop filter with capacitance multiplier
Noise consideration
REFERENCES
7 Other Building Blocks of PLL 151
151
151
152
155
156
161
162
164
164
171
173
176
176
178
7.1 VCO
7.1.1
7.1.2
7.1.3
7.1.4
7.1.5
LC-VCO
Varactor
Inductor
VCO phase noise
Layout
7.2
7.3
PHASE-FREQUENCY DETECTOR
CHARGE-PUMP
7.3.1
7.3.2
Reference spur
Charge pump architectures
7.4
7.5
7.6
PROGRAMMABLE DIVIDER
DIGITAL MODULATOR
CHIP LAYOUT
REFERENCES
8 Prototype Measurement Results 183
183
186
188
194
195
199
8.1
8.2
8.3
PRESCALER MEASUREMENT
LOOP FILTER MEASUREMENT
PLL MEASUREMENT
9 Conclusions
Appendix
REFERENCES
viii CMOS PLL Synthesizers: Analysis and Design
Index 213

joanhuo

为什么只有一部，另一部呢

joanhuo

part2 呢

joanhuo

不好意思，刚才错怪了。在这里表示道歉