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[资料] The effects of vias on PCB traces

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发表于 2007-4-6 14:10:22 | 显示全部楼层 |阅读模式
【文件名】:0746@52RD_The effects of vias on PCB traces.pdf
【格 式】:pdf
【大 小】:176K
【简 介】:
【目 录】:

Background:
Through the years we have worked with many engineers who have had strong feelings about the presence of vias on critical traces (such as fast rise time clock lines). These feelings have ranged from (a) the effects of vias are so negligible that they may be used freely, to (b) their effects are so significant that vias may not be used at all. Depending on your view, these two extremes place quite different constraints on PCB designs!
It is clear from the history of all the boards that have ever been designed in the past that vias have little impact at lower frequencies and rise times. It is only recently, as device rise times and timing issues caused by faster clock speeds have become critical PCB design issues, that the concern over a via's effect on PCB "transmission lines" has become a topic of discussion.
The perceived negative effects of vias may fall into one of several categories:
1. Vias are inherently capacitive and change the characteristic impedance of the trace.
2. Vias cause a step-function change in trace impedance and therefore cause reflections.
3. When a trace moves from one layer to another, it becomes referenced to a different reference plane, therefore severely distorting the characteristic impedance of the trace.
4. A trace can move to opposite sides of an individual reference plane without significant effect, but if it moves to a layer where it is referenced to a different plane then the characteristics of the transmission line are severely distorted.
5. The effect of the first via is the greatest,but the effects of additional vias diminish as more vias are added to the trace.

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发表于 2007-4-7 17:45:23 | 显示全部楼层
支持一下,文章不错!!
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发表于 2007-4-13 08:41:38 | 显示全部楼层
[em01][em01]
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发表于 2010-1-4 19:09:05 | 显示全部楼层
gooooooooooooooooooooooood
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