用VHDL实现键盘译码

lizhihai1122

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity jianpan is
port(clk:in std_logic;
     x:in std_logic_vector(3 downto 0);
     y:buffer std_logic_vector(1 downto 0);
     scan:out std_logic_vector(3 downto 0);
     dout1:out std_logic_vector(3 downto 0);
     dout2:out std_logic_vector(3 downto 0));
end;
architecture one of jianpan is
signal n,f:std_logic_vector(3 downto 0);
signal z:std_logic_vector(5 downto 0);
begin
process(clk)
begin
if clk'event and clk='1' then
y<=y+1;
case y is
when "00"=>scan<="1110";
when "01"=>scan<="1101";
when "10"=>scan<="1011";
when "11"=>scan<="0111";
when others=>scan<="1111";
end case;
end if;
end process;     
process(clk)
begin
  z<=y&x;
  if clk'event and clk='1' then
    case z is
      when "101011"=>n<="0000";
      when "000111"=>n<="0001";
      when "001011"=>n<="0010";
      when "001101"=>n<="0011";
      when "001110"=>n<="0100";
      when "010111"=>n<="0101";
      when "011011"=>n<="0110";
      when "011101"=>n<="0111";
      when "011110"=>n<="1000";
      when "100111"=>n<="1001";
      when others=>n<="ZZZZ";
    end case;
    end if;
    if clk'event and clk='1' then
    case z is
      when "101101"=>f<="1010";
      when "101110"=>f<="1011";
      when "110111"=>f<="0000";
      when others=>f<="ZZZZ";
    end case;
    end if;
    end process;
    dout1<=n;
    dout2<=f;
    end one;
   
功能有的还没有实现，请好心人补全！～！！！！！

yzyubo

[em09]虽然没啥用，但顶一下[em03]

cuitjxg

我用verilog实现了，有需要的朋友可以找我
QQ:112838599

gao72572

[em01]