编译遇到的问题!~望懂的指点下...

moon_lai

我的程序是这样的
entity two_consecutive is
port(clk,r,x:in bit;
  z:out bit);
end two_consecutive;
architecture dataflow of two_consecutive is
signal y1,y0: bit;
begin
state: block((clk='1' and not clk'stable) or r ='0')
begin
  y1<= guarded '0' when r='0' else x;
  y0<= guarded '0' when r='0' else '1';
end block state;
z<=y0 and ((not y1 and not x) or (y1 and x));
end dataflow;
可是,在编译时会提示如下错误..为什么啊?谁能帮我看看吗?[em13]
Error (10626): VHDL error at two_consecutive.vhd(12): can't implement clock enable condition specified using binary operator "or"
Error (10658): VHDL Operator error at two_consecutive.vhd(12): failed to evaluate call to operator ""or""
Error: Can't elaborate top-level user hierarchy
Error: Quartus II Analysis & Synthesis was unsuccessful. 3 errors, 0 warnings
Error: Processing ended: Sun Jan 07 11:10:29 2007
Error: Elapsed time: 00:00:03
Error: Quartus II Full Compilation was unsuccessful. 3 errors, 0 warnings

moon_lai

[em11]

moon_lai

我又做了一次实验..我把state: block((clk='1' and not clk'stable) or r ='0')中的"或"改成"与"就可以编译了..为什么呢?不是BLOCK里的保护语句就是BOOLEAN的值吗?为什么上面的语句会在编译时出错呢??想不通!~~[em10]