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发表于 2009-4-11 09:56:22
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Background:
Through the years we have worked with many
engineers who have had strong feelings abou
the presence of vias on critical traces (such as
fast rise time clock lines). These feelings have
ranged from (a) the effects of vias are so
negligible that they may be used freely, to (b)
their effects are so significant that vias may no
be used at all. Depending on your view, these
two extremes place quite different constraints
on PCB designs!
It is clear from the history of all the boards tha
have ever been designed in the past that vias
have little impact at lower frequencies and rise
times. It is only recently, as device rise times
and timing issues caused by faster clock
speeds have become critical PCB design
issues, that the concern over a via's effect on
PCB "transmission lines" has become a topic o
discussion. |
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