大家过来帮忙看看这个状态机

qscft · 发表于 2006-8-22 16:02:00

大家过来帮忙看看这个状态机

这几天我在调试一个状态机的时候碰到一些问题:
程序部分vhdl代码如下:
............................
.........................................
UC_SM_REGS: process (clk, reset)
begin
      if reset = RESET_ACTIVE then
            fft_state <= IDLE;
      elsif clk'event and clk = '1' then
            fft_state <= fft_next_state;
      end if;

end process;

fft_process1: process(clk_os, reset, result_rd_start, fft_state, outdataen)
begin
      if reset = RESET_ACTIVE then
            fft_next_state <= IDLE;
            ch0_rd_clk_en <= '0';
            ch0_rd_addr <= "1111111111";
            result_data_tmp <= "ZZZZZZZZZZZZZZZZ";
      else
            ch0_rd_clk_en <= '0';
            fft_start <= '0';
      case fft_state is
               when IDLE=>
         if  result_rd_start = '1' then          由另外一个状态机产生result_rd-start信号                   fft_start <= '1';
         end if;
      if  fft_start = '1' then
            fft_next_state <= CLK_EN;
      end if;

      when CLK_EN =>
         fft_start <= '1';
            ch0_rd_addr <= ch0_rd_addr + 1;

            if clk_os = '0' then
            ch0_rd_clk_en <= '1';
            fft_next_state <= IO_HANDLE;
      end if;
      when IO_HANDLE =>
         ch0_rd_clk_en <= '1';

      if  clk_os = '1' then
         result_data_tmp <= ch0_data_out;
         fft_next_state <= FFT_PROCESS;
      end if;
      when FFT_PROCESS=>
         fft_next_state <= SAVE_DATA;
      when SAVE_DATA=>
         fft_next_state <= CLK_END;
      when CLK_END =>
         if  clk = '1' then
            fft_next_state <= IDLE;
      end if;
      when others =>
      fft_next_state <= IDLE;
         end case;
   end if;

end process;

.............................
在用modelsim做时序仿真时发现状态机的状态在reset之后一个时钟时就变为unknown状态,  之后一直是unknown状态,状态机一直无法工作 ,下板看时也是这个情况

我用的是lattice的fpga ,状态机的functional simulation 是正确的,综合工具是synplify,开发环境isplevel6.0

工作频率是40MHz,

希望大家踊跃讨论,给兄弟一些启发和提示,谢谢
我是新手
[em13]

mazijin · 发表于 2006-8-22 19:42:00

if reset = RESET_ACTIVE then
fft_next_state <= IDLE;

这个有没有问题?

mazijin · 发表于 2006-8-22 19:43:00

我再看看

mazijin · 发表于 2006-8-22 19:47:00

[COLOR=#0000FF]UC_SM_REGS: process (clk, reset)
begin[52RD.com]
      if reset = RESET_ACTIVE then
            fft_state <= IDLE;
      elsif clk'event and clk = '1' then
            fft_state <= fft_next_state
      end if;
end process;[/COLOR][/COLOR]
修改为:
UC_SM_REGS: process (clk, reset)
begin
      if reset = RESET_ACTIVE then
            fft_state <= IDLE;
   end if;
      if clk'event and clk = '1' then
            fft_state <= fft_next_state
      end if;
end process;

mazijin · 发表于 2006-8-22 19:50:00

if reset = RESET_ACTIVE then[52RD.com]
            fft_next_state <= IDLE;[52RD.com]
            ch0_rd_clk_en <= '0';             [52RD.com]
            ch0_rd_addr <= "1111111111";[52RD.com]
            result_data_tmp <= "ZZZZZZZZZZZZZZZZ";[52RD.com]
      else[52RD.com]
            ch0_rd_clk_en <= '0';             [52RD.com]
            fft_start <= '0';

end if;[/COLOR]

mazijin · 发表于 2006-8-22 19:57:00

if reset = RESET_ACTIVE then
fft_next_state <= IDLE;
重复了吧?
两个进程里都有了啊

mazijin · 发表于 2006-8-22 19:59:00

if reset = RESET_ACTIVE then[52RD.com]
            fft_next_state <= IDLE;[52RD.com]
            ch0_rd_clk_en <= '0';             [52RD.com]
            ch0_rd_addr <= "1111111111";[52RD.com]
            result_data_tmp <= "ZZZZZZZZZZZZZZZZ";[52RD.com]
      else[52RD.com]
            ch0_rd_clk_en <= '0';             [52RD.com]
            fft_start <= '0';

这段是否可以搬到第一个进程里?

mazijin · 发表于 2006-8-22 20:04:00

if  result_rd_start = '1' then          由另外一个状态机产生result_rd-start信号                   fft_start <= '1';[52RD.com]
         end if;[52RD.com]
      if  fft_start = '1' then[52RD.com]
            fft_next_state <= CLK_EN;[52RD.com]
      end if;[52RD

个人认为这个也有点问题,应该改为:
if  result_rd_start = '1' then fft_start <= '1';fft_next_state <= CLK_EN
else fft_next_state <= IDLE;
end if;

mazijin · 发表于 2006-8-22 20:26:00

UC_SM_REGS1: process (reset)
begin
if reset = RESET_ACTIVE then  fft_state <= IDLE;
                              ch0_rd_clk_en <= '0';
                              ch0_rd_addr <= "1111111111";
                              result_data_tmp <= "ZZZZZZZZZZZZZZZZ";
else       ch0_rd_clk_en <= '0';
            fft_start <= '0';
end if;
end process;
--------------------------------------------------------------------
UC_SM_REGS2: process (clk)
begin
if clk'event and clk = '1' then  fft_state <= fft_next_state;
end if;
end process;
---------------------------------------------------------------------
fft_process1: process(clk_os, reset, result_rd_start, fft_state, outdataen)
begin
  case fft_state is
when IDLE=>if  result_rd_start = '1' then  fft_start <= '1';
            else fft_next_state <= IDLE;
            end if;
when CLK_EN =>fft_start <= '1';
               ch0_rd_addr <= ch0_rd_addr + 1;
               if clk_os = '0' then ch0_rd_clk_en <= '1';
                                    fft_next_state <= IO_HANDLE;
               else                fft_next_state <= CLK_EN;
               end if;
when IO_HANDLE =>ch0_rd_clk_en <= '1';
                  if  clk_os = '1' then  result_data_tmp <= ch0_data_out;
                                       fft_next_state <= FFT_PROCESS;
                  else                fft_next_state <= IO_HANDLE;
                  end if;
when FFT_PROCESS=>fft_next_state <= SAVE_DATA;
when SAVE_DATA=>fft_next_state <= CLK_END;
when CLK_END =>if  clk = '1' then
               fft_next_state <= IDLE;
               end if;
when others =>fft_next_state <= IDLE;
end case;
end if;
end process;

以上是我个人能力的极限了
小弟也刚学不久,今天刚好看到状态机设计这张书
菜得很,哈哈.

mazijin · 发表于 2006-8-22 20:27:00

楼主,对不起
灌烂了你的帖子

qscft · 发表于 2006-8-22 21:48:00

认真研读并修改中，谢谢各位，我试试

大家有什么新的想法尽管说出来，兄弟先谢了

qscft · 发表于 2006-8-22 21:53:00

第一个进程里是fft_state<=idle;

		自动登录	找回密码
密码			注册

[讨论] 大家过来帮忙看看这个状态机