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主要集中讨论IC设计中使用的防ESD的方法，layout的注意要点，IO接口设计，固定电压ESD，失效模式分析等。全文九大章节，共315页，内容极为翔实。为影印版英文，具体不多加介绍。免费给大家！52RD.com]
2RD.com]
小附目录一段：[52RD.com]
L.7 Y,, to- V} Core Clamps 161[52RD.com]
2.7.1. MDS Hased / 61[52RD.com]
2.7.2. Diode Clamps/ 62[52RD.com]
2.7.3. Cantilevered Diode / 68[52RD.com]
2.8_ CDM Guidelines / 71[52RD.com]
2.9. Summary / 79[52RD.com]
Referencm J SO[52RD.com]
ADDITIONAL ESO CON 51OCRATION5[52RD.com]
3.1[52RD.com]
3.2[52RD.com]
Capacitor Bm6ts in Stress Reduction / 81[52RD.com]
Packaging Effects oil ESA / 86[52RD.com]
3.2.1. Conventional Packaging J 86[52RD.com]
3.2.2. MU1tichip Modules / 90[52RD.com]
Small-Chip ESD issues 1 93[52RD.com]
Benefits of Distributed Clamps / 95[52RD.com]
Predriver Designs / 96[52RD.com]
3.3.[52RD.com]
3.4.[52RD.com]
3.5[52RD.com]
3.6. Antenna Diode Issues / 99[52RD.com]
3.7. Hot-Electron Interactions f 103[52RD.com]
3.8. Latchup Issues / l05[52RD.com]
3.9. Silicon-on-Insulator ESD Protection / 107[52RD.com]
3.10. Summary / 109[52RD.com]
References / 110[52RD.com]
4.1 D. Digital Compensation / 158[52RD.com]
4.11. Frequency-Based Compensation / 161[52RD.com]
4.12. Simultaneous Switching Output Naise / 162[52RD.com]
4.12.1_ Design for SSO Reduction / 168[52RD.com]
4.12.1.1. Predriver Skewing / 16&[52RD.com]
4.12_1.2. NP-Inverted Stack Driver / 169[52RD.com]
4.12.1.3. DlfererdW Signaling ,' 172[52RD.com]
4.12.1.4. SSO Reduction Using Packaging[52RD.com]
Options / 172[52RD.com]
4.12.1.5. SSO Reduction Using Loii-Weigi[52RD.com]
Coding / 173[52RD.com]
4.13. System Modeling / 174[52RD.com]
4.14. IJO lnfarmation on the Internet / 178[52RD.com]
4.15_ Summary / 174[52RD.com]
References } 180[52RD.com]
COM,6N,[52RD.com]
LAYOUT Issues[52RD.com]
5.1. Output Transistor Layout J 133[52RD.com]
5.2, Thick-Field Oxide (TFO) Layout / 19[52RD.com]
5.3. Diode Layout / 191[52RD.com]
5.4. Decoupling Capacitors / 192[52RD.com]
5.5. SCR Layout ) 196[52RD.com]
5.5. Antenna Diode Layout j 197[52RD.com]
5.7. Resistor Layouts / 197[52RD.com]
5.8. Periphery Layout / 202[52RD.com]
5.8.1. Power Delivery / 2112[52RD.com]
5.8.2 IJo Routing Channels / 206[52RD.com]
5_9. Metal Design [;uses J 207[52RD.com]
5.10. PSD Layout Verificatiou ! 212[52RD.com]
5.10.1. Manual PSD Veri&catiox[52RD.com]
5.10_2. Automated Verification[52RD.com]
5.11. Summary / 213[52RD.com]
References 1 214[52RD.com]
eso near 110 INTERACTIONS[52RD.com]
6-1. V0 Pcifotxnance Trade-off 1 219[52RD.com]
6.1.1- impact on Output Buffer[52RD.com]
6-1.2, Impact on Compensation[52RD.com]
Implementation 1 220[52RD.com]
Input Pass Transistor Jitters[52RD.com]
OthcrInleractions / 224[52RD.com]
rv Noise Cannon. ;nfn !'n,n[52RD.com]
rln[52RD.com]
Snpvlics r z26[52RD.com]
120 and Corc Switching Current[52RD.com]
Characterisrirc 1 '177[52RD.com]
Peripheral Noise Coupling ThrouSf[52RD.com]
FSn no-l- ) iie[52RD.com]
5.2.3. Peripheral IYoiss anc[52RD.com]
Lnterartinn 1 711[52RD.com]
Power System imvcdarnca[52RD.com]
ESD Diodes and I/4 Signal Integrity / 233[52RD.com]
6.3.1. High-Frequency Leakage in LJD f 24:[52RD.com]
6.3[52RD.com]
R} }ow.ee 17A.[52RD.com]
-nwl[52RD.com]
MIXED-VOLTAQ6 ESD 2-[52RD.com]
7.1, Mixed-Voltage Input Design 1 246[52RD.com]
7.1.1. Input Design for Low-VOSWE Core and[52RD.com]
High-Voltage 1/O / 246[52RD.com]
7,1,2_ Input Design far High-Voltage Core and[52RD.com]
Low-Voltage 1/0 17.55[52RD.com]
7.1.3. Capacidve-COUpled Input Receiver / 7.56[52RD.com]
7.2. Output Design for Mixed Voltage j 257[52RD.com]
7.2_ L Opcn-Dwain Design for High-Voltage 110 / 258[52RD.com]
7,2,2. CMOS Buffcr Design for Higb-Voltage 1/O 1260[52RD.com]
7.2.3. Output Predrirars for High-Voltage 1/O 1 263[52RD.com]
7,3- Effect on power Supply Coupling Diodes 1 264[52RD.com]
7.4. Separate FSD Bus j 266[52RD.com]
7.5. Back Biasing / 269[52RD.com]
7.6. Process Modifications to Support High Voltages / 272[52RD.com]
7.7. Summary / 273
【文件名】:06812@52RD_06810@52RD_Basic ESD And IO Design[1].part1.rar
【格 式】:rar
【大 小】:4000K
【简 介】:
【目 录】:
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