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[资料] 高通PCB Layout Guidelines

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签到天数: 48 天

[LV.5]常住居民I

发表于 2017-2-28 17:33:01 | 显示全部楼层 |阅读模式
1 Introduction...................................................................................................... 6
1.1 Purpose and intended audience..................................................................................... 6
1.2 Documentation overview.............................................................................................. 6
1.3 Terms and acronyms ..................................................................................................... 8
2 Layout Strategy ............................................................................................... 9
2.1 Parts placement and signal flow ................................................................................... 9
2.2 Shielding ..................................................................................................................... 12
2.3 PCB stack-up .............................................................................................................. 14
2.4 Using vias ................................................................................................................... 14
2.5 Grounding ................................................................................................................... 15
3 PCB Considerations...................................................................................... 16
3.1 Number of layers and PCB stack-up........................................................................... 16
3.2 Assigning functions to each layer ............................................................................... 17
3.3 RF traces: controlled-impedance transmission lines................................................... 18
3.3.1 Example microstrip design................................................................................ 19
3.3.2 Example stripline design ................................................................................... 20
3.4 Vias ............................................................................................................................. 21
3.5 Grounding ................................................................................................................... 23
3.6 Component land patterns ............................................................................................ 24
4 Example Reference Design........................................................................... 25
4.1 High-level layout concept ........................................................................................... 25
4.2 Stack-up and layer descriptions .................................................................................. 27
4.2.1 Layer 1 description............................................................................................ 27
4.2.2 Layer 2 description............................................................................................ 28
4.2.3 Layer 3 description............................................................................................ 30
4.2.4 Layer 4 description............................................................................................ 32
4.2.5 Layer 5 description............................................................................................ 32
4.2.6 Layer 6 description............................................................................................ 33
5 Specific Layout Guidelines........................................................................... 34
5.1 RF signals ................................................................................................................... 34
5.1.1 General RF guidelines ....................................................................................... 34
Fundamentals of PCB Layout Guidelines for radioOne® Designs Application Note Contents
80-V9813-1 Rev. A 3 QUALCOMM Proprietary
5.1.2 Clearing ground below RF traces and pads....................................................... 36
5.1.3 GPS circuits and signals .................................................................................... 36
5.1.4 Front-end circuits and signals............................................................................ 37
5.1.5 RFIC matching networks................................................................................... 38
5.2 LO-related circuits and signals ................................................................................... 40
5.2.1 LO signals (at UHF) .......................................................................................... 40
5.2.2 VCO tuning lines............................................................................................... 41
5.2.3 TCXO distribution............................................................................................. 42
5.3 Baseband Rx and Tx signals ....................................................................................... 43
5.4 Digital signal traces .................................................................................................... 44
5.4.1 PDM signals: TX_AGC_ADJ and TRK_LO_ADJ........................................... 44
5.4.2 SBI signals......................................................................................................... 44
5.4.3 Other digital signals........................................................................................... 45
5.5 DC power.................................................................................................................... 46
5.5.1 PA power supply distribution............................................................................ 46
5.5.2 Power supply traces routed under RFICs .......................................................... 47
6 Other Board-level Considerations ............................................................... 49
6.1 Radiated desensitization.............................................................................................. 49
6.1.1 Desensitization due to the CHIPx16 45th harmonic .......................................... 49
6.1.2 Desensitization due to the TCXO 46th harmonic............................................... 50
6.1.3 Desensitization due to LCD and camera interface ............................................ 53
6.2 GPS functions ............................................................................................................. 54
6.3 Thermal considerations............................................................................................... 54
7 Layout Checklist............................................................................................ 56

签到天数: 221 天

[LV.7]常住居民III

发表于 2017-3-2 13:07:32 | 显示全部楼层
没有附件~~~~~~~
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发表于 2017-3-2 16:14:24 | 显示全部楼层
没有附件
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签到天数: 430 天

[LV.9]以坛为家II

发表于 2017-3-3 10:10:08 | 显示全部楼层
我有,赚点R币

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签到天数: 98 天

[LV.6]常住居民II

发表于 2017-3-5 14:10:35 | 显示全部楼层
感谢分享
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签到天数: 10 天

[LV.3]偶尔看看II

发表于 2017-3-5 20:23:38 | 显示全部楼层
顶顶顶顶顶

签到天数: 826 天

[LV.10]以坛为家III

发表于 2017-3-6 10:34:54 | 显示全部楼层
附件在哪呢?和4楼的一样吗?

签到天数: 20 天

[LV.4]偶尔看看III

发表于 2017-3-7 10:52:54 | 显示全部楼层
附件在哪呢?和4楼的一样吗?

签到天数: 34 天

[LV.5]常住居民I

发表于 2017-7-24 09:51:55 | 显示全部楼层
下载一半,怎么也下载不下来啊

签到天数: 5 天

[LV.2]偶尔看看I

发表于 2017-7-25 17:51:06 | 显示全部楼层
感谢分享
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[LV.1]初来乍到

发表于 2018-6-11 12:40:59 | 显示全部楼层
不错,这个如果是集成在一起做成模块后对PCB layout的要求就没有那么严了吧,就是一个普通板了吧

签到天数: 9 天

[LV.3]偶尔看看II

发表于 2019-7-6 16:29:00 | 显示全部楼层
谢谢谢谢谢谢

签到天数: 1 天

[LV.1]初来乍到

发表于 2019-7-8 22:37:20 | 显示全部楼层
感謝分享, 學習學習
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