Symbol synchronization technique in COFDM systems

Sophie

【文件名】:0669@52RD_bol synchronization technique in COFDM systems.rar
【格　式】:rar
【大　小】:184K
【简　介】:Abstract—In this paper we focus our research on the symbol
timing synchronization technique in COFDM systems. A new
method utilizing pilots to do coarse symbol timing is proposed.
It overcomes the problem of fluctuation of the estimated symbol
start position with cyclic prefix correlation method. The symbol
timing error with the proposed method is within only 10
samples. Different from the algorithms in [1]–[3], we utilize the
known pilot information to estimate the residual symbol timing
offset with low system complexity. This paper also proposes a new
control model for the sampling clock adjustment, different from
the phase-locked loop (PLL) [4], [5] or delay-locked loop (DLL) [2]
method. The simulation and correspondent Field Programmable
Gate Array (FPGA) circuit through test in HDTV prototype in
Team of Engineering Expert Group (TEEG) proves its feasibility
and availability. The proposed method is also suitable for burst
mode transmission systems such as Wireless Local Area Network
(WLAN) and Fixed-Broadband Wireless Access (F-BWA).

【目　录】:
I. INTRODUCTION
II. SYMBOL TIMING SYNCHRONIZATION
III. PROPOSED SYMBOL TIMING SYNCHRIONIZATION MODEL
IV. CONCLUSION