可综合的Verilog语法

Gill

【文件名】:06518@52RD_可综合的Verilog语法（剑桥大学，影印）[1].p.rar
【格　式】:rar
【大　小】:299K
【简　介】:Synthesizable Verilog is a subset of the full Verilog HDL [9] that lies within the domain of current synthesis tools (both RTL and behavioral).
This document species a subset of Verilog called V0.1 This subset is intended as a vehicle for the rapid prototyping of ideas.
【目　录】:
1 Syntax 1
2 Semantic Pseudo-Code 5
3 Event Semantics 13
4 Trace Semantics 25
5 Cycle Semantics

bobodu

<P>怎么都要RDB啊，看不了</P>[em03]

oxford

<P>支持一下看看。</P>

vfdff

钱怎么赚呀！！下不了

casson_1

ding!!怎么赚钱？？