Logic Synthesis 策略选择及对比

Patricia

【文件名】:06511@52RD_Logic Synthesis 策略选择及对比.rar
【格　式】:rar
【大　小】:96K
【简　介】:A wealth of new hierarchical compile strategies have become available in the last few years. This paper will compare area, speed, and compile time for several large designs using a variety of hierarchical compile strategies: top-down compile, top-down simple compile, bottom-up with
default constraints, bottom-up with hand-crafted constraints, and ACS (Automated Chip Synthesis).
【目　录】:
1.0 Introduction
2.0 Example design
3.0 Software and hardware
4.0 Compile strategies
5.0 Results
6.0 Results from larger design: cpu_X2
7.0 Results from larger design: cpu_X5
8.0 Results from larger design: cpu_X10