DESIGN OF CMOS FRONT END FOR A RF RECEIVER

benever

Radio frequency design has been one of the principal research areas in the recent
past. Emergence of several RF Wireless Communication standards of communication
has demanded availability of low cost analog blocks for use in transceiver.
Particularly, lot of research has undergone in CMOS technology, due to its low cost
nature. In this project, we have tried to design a front-end element for a RF receiver.
The front design involves at least two components the low noise amplifier and the
mixer. Both the blocks have been designed and simulated as part of this project.
Several factors are needed to be considered for such designs, as majority of low
frequency fundamentals, are not very much valid at high frequency. Particularly, the
effect of noise, parasitics and passive devices needs special consideration. Passive
devices were studied as one full part of the project, leading to design of a small
software for inductor's value calculation from geometry parameters. Noise
components of MOS at high frequencies were studied in detail. In design of low noise
amplifier, these studies were extensively used. In this design, we concentrated our
efforts on minimizing the value of passive devices so that all of them can be fabricated
on single chip. For this we undertook several optimizations and tradeoffs. Particularly
the noise power tradeoff with inductors' value was stressed on. LNA had three primary
design specifications of input impedance matching, gain and noise. We also
experimented on several techniques of input match. The results obtained by us suited
to our needs fairly well.
【文件名】:12118@52RD_DESIGN OF CMOS FRONT END FOR A RF RECEIVER.pdf
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