Automated Pipelining in ASIC Synthesis Methodology

Germaine

【文件名】:06510@52RD_Automated Pipelining in ASIC Synthesis Methodology Gate Transfer [1]....rar
【格　式】:rar
【大　小】:358K
【简　介】:Register Transfer Level (RTL) synthesis method
simplified clocked circuitry design and allowed its
automation by effectively separating logic
optimization from timing. This boosted VLSI
industry for more than a decade. However, process
variation, signal integrity problems and others
physical limitations of synchronous designs are
encouraging a search for alternative solutions.
Synchronous design is turning out now to become
a costly proposition. ITRS has noticed this trend
and cited an impending crisis. It predicts that in the
near future, the industry will be able to
manufacture chips so complex that timing analysis
issues will become completely intractable,
requiring a shift from traditional synchronous to
asynchronous architecture [1].
【目　录】:
1. Introduction
2. Implementation Basics
3. Design flow
4. Weaving: case study
5. Preliminary experimental results
6.Conclusion and future work