状态机及综合的文章

Veronica

【文件名】:0659@52RD_状态机的论文.rar
【格　式】:rar
【大　小】:113K
【简　介】:Abstract†: Designing a synchronous finite state
machine (FSM) is a common task for a digital logic
engineer. This paper will discuss a variety of issues
regarding FSM design using Synopsys Design
Compiler1. Verilog and VHDL coding styles will be
presented. Different methodologies will be compared
using real-world examples.
【目　录】:
1.0 Introduction
2.0 Basic HDL coding
3.0 State assignment
4.0 Coding state transitions
5.0 Outputs
6.0 Inputs
7.0 FSM extract
8.0 Timing constraints
9.0 Synthesis strategies
10.0 Compile results
11.0 Hints, tips, tricks, mysteries
12.0 Acknowledgments
13.0 References

Veronica

【文件名】:0659@52RD_综合问题.rar
【格　式】:rar
【大　小】:52K
【简　介】:One of the most misunderstood constructs in the Verilog language is the nonblocking assignment. Even very experienced Verilog designers do not fully understand how nonblocking assignments are scheduled in an IEEE compliant Verilog simulator and do not understand when and why nonblocking assignments should be used. This paper details how Verilog blocking and
nonblocking assignments are scheduled, gives important coding guidelines to infer correct synthesizable logic and details coding styles to avoid Verilog simulation race conditions.
【目　录】:
1.0 Introduction
2.0 Verilog race conditions
3.0 Blocking assignments
4.0 Nonblocking assignments
5.0 Verilog coding guidelines
6.0 The Verilog "stratified event queue"