system verilog 的几篇文章

Helgain

【文件名】:0658@52RD_System Verilog.rar
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【简　介】:一、The Accellera SystemVerilog 3.0 Standard[11], released at DAC 2002, includes many enhancements to the IEEE Verilog-2001 hardware description language[7]. A few of these enhancements were added to assist in the efficient development of Finite State Machine (FSM) designs.
The SystemVerilog enhancements were not only added to improve RTL coding capability, but also to improve simulation debug and synthesis capabilities.
Before you can code an efficient FSM design using SystemVerilog 3.0 RTL enhancements, you need to know how to code efficient Verilog-2001 FSM designs. Section 2.0 shows efficient Verilog-2001 styles for coding FSM
designs and Sections 10.0 shows and details SystemVerilog enhancements for FSM design.
Section 8.0 also details Synopsys DC 2002.05 FSM Compiler enhancements and their impact on standard FSM designs.
二、I have been very active in Verilog design and standards activities for over a decade, have done both Verilog and VHDL synthesis design and have done detailed examinations of the virtues and pitfalls of Verilog and VHDL. Based on my experience, I believe that SystemVerilog is a revolutionary step forward in the evolution of hardware description and verification languages.
In this paper I will discuss the many features of SystemVerilog that were inspired by VHDL.
VHDL is not a dead language. VHDL, along with Verilog, lives in a powerfully enhanced HDL called SystemVerilog.
Should SystemVerilog really be called SystemHDL? Perhaps. But since the core syntax of the language is rooted in the Verilog HDL, the name of the enhanced language bears the Verilog moniker. Any VHDL engineer that claims that SystemVerilog should really be called SystemHDL will receive little argument from me.
三、Verilog-2001 introduced an enhanced and abbreviated
method to declare module headers, ports and data types.
The Accellera SystemVerilog effort will further enhance
Verilog design by abbreviating the capability to
instantiate modules with implicit port connections and
interface types. These capabilities and additional
complimentary enhancements are detailed in this paper.

【目　录】:
一、1.0 Introduction
2.0 Review of standard Verilog FSM coding styles
3.0 fsm7 Example - 2 inputs, 1 output, 10 states and 20 transition arcs
4.0 fsm8 Example - 4 inputs, 3 outputs, 10 states and 26 transition arcs
5.0 prep4 Example - 8-bit input, 8-bit output, 16 states and 40 transition arcs
6.0 Coding benchmarks for standard FSM coding styles
7.0 Synthesis benchmarks for standard FSM coding styles
8.0 DC-Ultra 2002.05 FSM Tool
9.0 Verliog-2001 Enhanced Coding Styles
10.0 SystemVerilog enhancements
11.0 Implicit port connections
12.0 FSM coding with SystemVerilog 3.0
13.0 Ask your vendor to support SystemVerilog, NOW!
14.0 Conclusions
二、1.0 Introduction
2.0 VHDL Features - Not in Verilog - Added to SystemVerilog
3.0 Notable VHDL Constructs Missing from SystemVerilog
4.0 Features requested for VHDL-200x
5.0 Additional SystemVerilog Features Not Found in VHDL
6.0 EDA Tool Support
7.0 Conclusions
8.0 Acknowledgements
三、1. Introduction
2. Verilog-1995: verbose module headers
3. Verilog-2001: “ANSI-C” style ports
4. Verilog-2001: `default_nettype none
5. SystemVerilog: Implicit port connections
6. SystemVerilog: interface port types
7. SystemVerilog Proposals
8. Summary and conclusions