Guidelines For Introduction Design Synthesis Using Design Compiler

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【文件名】:0658@52RD_SynthGuidelines-Akella-021018.rar
【格　式】:rar
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【简　介】:
One of the most important steps in ASIC design is the synthesis phase. Synthesis is an automatic method of converting a higher level of abstraction to a lower level of abstraction. In other words the synthesis process converts Register Transfer Level (RTL) descriptions to gate-level netlists. These gate-level netlists can be optimized for area,speed, testability, etc. The synthesis process is shown in Fig 1.0.
The inputs to the synthesis process are RTL HDL description, circuit constraints and attributes for the design, and a technology library. The synthesis process produces an optimized gate-level netlist from all these inputs. Synthesizing a design is an iterative process and begins with defining the constraints for each block of the design. In addition to these constraints, a file defining the synthesis environment is also needed. The environment file specifies the technology cell libraries and other relevant information that
the tool uses during synthesis.
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