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简要介绍:
An improved digital intermediate frequency (IF) transmitter architecture for wide-band code-division multipleaccess(W-CDMA) mobile terminals is proposed. Based on the
heterodyne design but without requiring any off-chip IF filter,the transmitter enjoys the advantages of a homodyne architecture (such as circuit simplicity, low power consumption, and a high level of integration) while avoiding the performance problems
associated with direct upconversion. By implementing the quadrature modulation in the digital domain and requiring only a single path of analog baseband circuits, inherently perfect I/Q matching and good error vector magnitude (EVM) performance can be achieved. The IF is chosen to be a quarter of the clock rate for a very simple and low-power digital modulator design. The difficulties of on-chip IF filtering were greatly alleviated by 1) performing a careful frequency planning and 2) employing a special-purpose digital-to-analog converter to produce high-order sin(x)/x rolloff. System-level simulation demonstrates that spurious-emission requirements are met with virtually no dedicated reconstruction filter circuits. This architecture takes full advantage of complimentary metal–oxide–semiconductor technology scaling by employing digital processing to ease analog complexities.
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