VerificationMethodology_W

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【文件名】:06427@52RD_4442_Unified_VerificationMethodology_WP1.rar
【格　式】:rar
【大　小】:112K
【简　介】:The unified verification methodology addresses the most critical verification challenges, while maximizing overall speed and efficiency. The methodology is centered on the creation and use of a transaction-level golden representation of the design and verification environment called the functional virtual prototype (FVP). The methodology encompasses all phases of the verification process and crosses all design domains. Utilizing the
unified verification methodology will enable development teams to attain their verification goals on time.
While focusing on the verification of systems-on-a-chip (SoCs) the methodology also encompasses verification of individual subsystems. Large application-specific digital or analog designs are often first developed as standalone components and later used as SoC subsystems. The unified verification methodology can be applied in whole to a SoC design or in parts for more application-specific designs. Different designs and design teams will emphasize different aspects of a methodology. The unified verification methodology will produce the greatest gains in speed and efficiency when used in a complete top-down integrated manner. It is understood that a complete top-down flow may not always be feasible for a number of different reasons. Thus the methodology is flexible in providing for both top-down and bottom-up approaches to developing subsystems while still providing an efficient top-down verification methodology.
【目　录】:
1 INTRODUCTION
2 KEY CONCEPTS
3 PLATFORM REQUIREMENTS
4 SOC METHODOLOGY
5 CONTROL-BASED DIGITAL SUBSYSTEMS
6 ALGORITHMIC-BASED DIGITAL SUBSYSTEM
7 ANALOG SUBSYSTEM
8 EVOLUTIONARY MIGRATION STRATEGY