层次化验证

Lucinda

【文件名】:Testbench Design, A Systematic Approach[1]..rar
【格　式】:rar
【大　小】:88K
【简　介】:This paper describes a systematic method to architect a system-level testbench for functional verification of complex multi-function System on a Chip (SoC). This systematic approach can reduce the overall effort expended on verification. The testbench architecture uses a layered approach to increase the level of abstraction on which to write tests.
【目　录】:
1 Introduction
2 Testbench Architecture: A Systematic Layered Approach
3 Experimental Results
4 Conclusions
5.Audience Prerequisites

Lucinda

【文件名】:06427@52RD_Verification Intellectual Property (IP)Modeling Architecture.rar
【格　式】:rar
【大　小】:147K
【简　介】:made it possible for electronic system designers to assemble complete systems-on-chips (SoC).As these System on chips have found their use in more and more computer, graphics, and networking hardware systems the level and complexity of functionality within them have dramatically increased. At the same time shrinking time to market leaves little room for errors in the design. Hence functional verification has become one of the major tasks in committing chips to fabrication. Just as designs are pushing more towards reusable and portable environment so must the verification components and environment. Also, more technologically advanced and high-pin packages allow each chip to have multiple bus interfaces, each of which
may share internal resources in parallel and increase the possible concurrent operations.
Therefore there has arisen a real and pressing need in the electronic design process for standalone,pre-verified and built-in verification infrastructure, which can be easily plugged in the simulation-based validation tests. The Verification Intellectual Property (Verification IP) is an integral and important component of such infrastructure and provides such mechanisms.
【目　录】:无目录