书写好的代码

Wesleyren

【文件名】:06412@52RD_Writing Successful RTL descriptions in Verilog.rar
【格　式】:rar
【大　小】:69K
【简　介】:This paper discusses a few techniques for writing successful RTL descriptions in Verilog
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While Verilog is the language used in the examples, some of the ideas are also applicable to other HDL languages, such as VHDL.
The use of structure to control the synthesis process is the main ingredient for success when writing RTL descriptions. Structure is defined as the way in which parts are arranged or put together to form a whole, and it is created through the use of modules and cell instantiation.
The designer should code the RTL to reflect the desired hardware structure. Why use Verilog HDL instead of schematic capture? The main reason is to make the logic designer more productive.
Quality is also improved because more time can be spent on logic verification rather than on the detailed gate-level implementation. And a more concise and readable design makes it easier for the design to be reused by others.
【目　录】:无目录