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有高手能讲解下用bluelab开发应用程序的一般步骤吗？没有一个很好的教程啊，
看了一段时间的资料了，但是还是没能够对BC05有个整体的概念。
想在这个芯片上做一个语音识别的小系统，但是不知道应该怎么下手。
我查到网上的语音程序基于C语言的有调用像BSR_train()函数的程序，这种调用库函数的程序能编写在基于BC05的系统里边吗？
还是只能用bluelab的库函数？
还希望能提供以下库的一份汉语说明就好了。谢谢啊。
后边附一些资料吧
【文件名】:11613@52RD_BlueCore5KalimbaDSP_User_GuideCS-101693-UGP4---打印.pdf
【格 式】:pdf
【大 小】:2879K
【简 介】:The _äìÉ`çêÉΔRJjìäíáãÉÇá~ Kalimba DSP User Guide is for developers of software applications and algorithms for
the DSP (Digital Signal Processor) co-processor on the BlueCore5-Multimedia device. It documents the
architecture of the Kalimba DSP, instruction set mnemonics and peripheral features, and includes some example
code. Read this document in conjunction with the other Kalimba tools documents that are available:
􀂃 BlueLab Kalimba DSP Assembler User Guide which describes the assembler software
􀂃 BlueLab xIDE User Guide which describes xIDE, the software debugging tool
One of the features of the BlueCore5-Multimedia device is an on-chip DSP co-processor, Kalimba. The Kalimba
DSP particularly targets audio processing applications for BlueCore. The likely audio processing applications
include:
􀂃 Sub-Band Coding (SBC) encoding and decoding, as defined in the Bluetooth Advanced Audio
Distribution Profile
􀂃 MP3 encoding and decoding, as defined in ISO/IEC 11172-3, and the sample rate extensions defined in
ISO/IEC 13818-3
􀂃 Advanced Audio Coding (AAC) encoding and decoding, as defined in ISO/IEC 13818-7
􀂃 Alternative voice/Hi-Fi CODECs
􀂃 Echo and noise cancellation
􀂃 Audio signal enhancement
􀂃 Stereo enhancement
􀂃 Equaliser
􀂃 Lost packet concealment
􀂃 Text to speech
􀂃 Voice recognition
【目 录】:Contents
1 Introduction ................................................................................................................................................... 6
2 Key Features ................................................................................................................................................. 7
3 System Overview .......................................................................................................................................... 8
3.1 Kalimba DSP Core ................................................................................................................................. 9
3.2 Kalimba DSP Memory ............................................................................................................................. 9
3.3 Kalimba DSP Peripherals ........................................................................................................................ 9
3.3.1 Memory Management Unit Interface ............................................................................................9
3.3.2 Programmable I/O Control ........................................................................................................... 9
3.3.3 Interrupt Control ........................................................................................................................... 9
3.3.4 Clock Source Select and Timer.................................................................................................... 9
3.3.5 Debug Interface........................................................................................................................... 9
4 Kalimba DSP Core Architecture ................................................................................................................. 10
4.1 Arithmetic Logic Unit............................................................................................................................. 10
4.2 Address Generators .............................................................................................................................. 10
4.3 Registers .............................................................................................................................................. 11
4.4 Bank 1 Registers .................................................................................................................................. 11
4.5 rFlags Register ..................................................................................................................................... 12
4.5.1 Negative Flag (N) ....................................................................................................................... 12
4.5.2 Zero Flag (Z) .............................................................................................................................. 12
4.5.3 Carry Flag (C) ............................................................................................................................ 12
4.5.4 Overflow Flag (V) ....................................................................................................................... 12
4.5.5 Sticky Overflow Flag (SV) .......................................................................................................... 13
4.5.6 User Definable Flag (UD)........................................................................................................... 13
4.5.7 Bit Reverse Flag (BR) ................................................................................................................ 13
4.5.8 User Mode Flag (UM)................................................................................................................. 13
4.5.9 Condition Codes......................................................................................................................... 13
4.6 rMAC Register ...................................................................................................................................... 14
4.7 Bank 2 Registers .................................................................................................................................. 14
4.7.1 Index Registers .......................................................................................................................... 15
4.7.2 Modify Registers ........................................................................................................................ 15
4.7.3 Length Registers ........................................................................................................................ 15
4.8 Special Bank 3 registers....................................................................................................................... 15
4.9 Stalls .................................................................................................................................................. 16
4.10 Prefixes................................................................................................................................................. 17
4.11 Circular Buffers..................................................................................................................................... 18
4.12 Zero Overhead Looping: do卨oop ........................................................................................................ 19
4.13 Debug .................................................................................................................................................. 20
5 Memory Organisation ................................................................................................................................. 21
5.1 Memory Map......................................................................................................................................... 21
5.1.1 PM Memory Map........................................................................................................................ 22
5.1.2 DM1 Memory Map...................................................................................................................... 22
5.1.3 DM2 Memory Map...................................................................................................................... 23
6 Instruction Set Description ......................................................................................................................... 24
6.1 ADD and ADD with CARRY................................................................................................................... 25
6.2 SUBTRACT and SUBTRACT With Borrow............................................................................................ 26
6.3 Bank 1/2 Register Operations: ADD and SUBTRACT........................................................................... 27
6.4 Logical Operations: AND, OR and XOR................................................................................................ 28
6.5 Shifter: LSHIFT and ASHIFT ................................................................................................................. 29
6.6 rMAC Move Operations ......................................................................................................................... 30
6.7 Multiply: Signed 24-Bit Fractional and Integer ....................................................................................... 31
Contents
CS-101693-UGP4
(bc05-ug-001P)
?Cambridge Silicon Radio Limited 2006-2008
This material is subject to CSR抯 non-disclosure agreement. Page 3 of 95
_潇蒨珀蒖Jj熹磲闵轻~ Kalimba DSP User Guide
6.8 MULTIPLY and ACCUMULATE (56-bit) ................................................................................................ 31
6.9 LOAD / STORE with Memory Offset...................................................................................................... 33
6.10 Sign Bits Detect and Block Sign Bits Detect .......................................................................................... 34
6.11 Divide Instruction .................................................................................................................................. 35
6.12 PUSH, POP and PLOOK Stack Instructions.......................................................................................... 36
6.13 Program Flow: CALL, JUMP, RTS, RTI, SLEEP, DO...LOOP and BREAK........................................... 37
6.14 Indexed MEM_ACCESS_1 and MEM_ACCESS_2............................................................................... 38
7 Instruction Coding ...................................................................................................................................... 39
7.1 Type A Instruction................................................................................................................................. 40
7.2 Type B Instruction................................................................................................................................. 40
7.3 Type C Instruction ................................................................................................................................ 40
7.4 Special Cases....................................................................................................................................... 40
7.5 OP_CODE Coding................................................................................................................................ 41
7.6 AM Field ............................................................................................................................................... 42
7.7 Carry Field (C Field) .............................................................................................................................. 42
7.8 Bank 1/2 Register Select Field (B2RS Field) ......................................................................................... 42
7.9 Saturation Select Field (V Field) ............................................................................................................ 42
7.10 Sign Select Field (S Field) ..................................................................................................................... 43
7.11 k16 Coding for LSHIFT and ASHIFT....................................................................................................... 43
7.12 rMAC Sub Registers............................................................................................................................. 43
7.13 ASHIFT................................................................................................................................................. 43
7.14 LSHIFT ................................................................................................................................................. 44
7.15 k16 Coding Divide Instructions................................................................................................................ 44
7.16 StackBankSelect field encoding ............................................................................................................ 45
8 Kalimba DSP Peripherals ............................................................................................................................ 46
8.1 MMU Interface ...................................................................................................................................... 47
8.1.1 Read Ports ................................................................................................................................ 47
8.1.2 Write Ports ................................................................................................................................ 47
8.2 DSP Timers .......................................................................................................................................... 47
8.3 Kalimba Interrupt Controller................................................................................................................... 48
8.3.1 DSP Core Functionality During Interrupt .................................................................................... 48
8.3.2 Interrupt Controller Functionality ................................................................................................ 48
8.4 Generation of MCU Interrupt ................................................................................................................. 49
8.5 PIO Control........................................................................................................................................... 49
8.6 MCU Memory Windows in DM2............................................................................................................. 49
8.7 Flash Memory Windows in DM2 ............................................................................................................ 49
8.8 PM Window in DM1 ............................................................................................................................... 50
8.9 PM Flash Window with 64-word Direct Cache....................................................................................... 50
8.10 MCU I/O Map Memory-Mapped Interface.............................................................................................. 50
8.11 General Registers................................................................................................................................. 50
8.12 Clock Rate Divider Control .................................................................................................................... 50
8.13 Debugging ...............................................................................................................................
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