Verilog Coding Style for Efficient Dightal Design

roxannera

【文件名】:0647@52RD_Verilog Coding Style for Efficient Dightal Design.zip
【格　式】:zip
【大　小】:82K
【简　介】:In this paper, we discuss efficient coding and design styles using verilog. This can be
immensely helpful for any digital designer initiating designs. Here, we address different problems ranging
from RTL-Gate Level simulation mismatch to race conditions in writing behavioral models. All these
problems are accompanied by an example to have a better idea, and these can be taken care off if these
coding guidelines are followed. Discussion of all the techniques is beyond the scope of this paper, however,
here we try to cover a few of them.
【目　录】:
1. Reading a variable before assigning - Simulation and Synthesis mismatch
2. Using the sensitivity lists
3. Full Case Parallel Case
4. Race Condition
5. Conclusion