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Title: ASIC Design Leader
Job Description:
1. Participate SoC design from architecture define to final netlist, feedback to Physical Design team to help to close timing and check floorplan;
2. Write ASIC specific part of test plans to prove functional correctness from block level to SoC level;
3. Take part in FPGA verification;
4. Co-work with HW/SW on system bring-up and debugging;
5. Maintain design environment, solve flow issues, and develop scripts to improve flow efficiency.
Qualification:
1. Master degree or above in EE;
2. 5+ years of hands-on experience and 2+ success SOC tap out stories;
3. Must have at least one excellent background on following area(ARM, DDR2/DDR3,Video/Audio process,USB,Ethernet)
4. Good macro-architecture design and RTL coding skills;
5. Familiar with ASIC design flow, including Simulation/Debug/Synthesis/STA/DFT
6. Hands-on Experience on PERL,TCL etc.script language;
7. Team spirit and a good communication skill.
MSN:Eileen.wang@live.cn
E-mail:eileenwang2010@163.com |
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