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发表于 2006-3-29 23:35:00
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<P>內容簡介如下</P><P>Preface
About this manual .................................................................................... xxviii
Feedback ................................................................................................. xxxiii
Chapter 1 Introduction
1.1 About the ARM1136JF-S processor ........................................................... 1-2
1.2 Components of the processor ..................................................................... 1-3
1.3 Power management .................................................................................. 1-23
1.4 Configurable options ................................................................................. 1-25
1.5 Pipeline stages .......................................................................................... 1-26
1.6 Typical pipeline operations ....................................................................... 1-28
1.7 ARM1136JF-S architecture with Jazelle technology ................................. 1-34
1.8 ARM1136JF-S instruction set summary .................................................... 1-36
1.9 Product revisions ...................................................................................... 1-56
Chapter 2 Programmer’s Model
2.1 About the programmer’s model ................................................................... 2-2
2.2 Processor operating states ......................................................................... 2-3
2.3 Instruction length ......................................................................................... 2-4
2.4 Data types ...................................................................................................2-5
2.5 Memory formats .......................................................................................... 2-6
2.6 Addresses in an ARM1136JF-S system ..................................................... 2-8
2.7 Operating modes ........................................................................................ 2-9
2.8 Registers .................................................................................................. 2-10
2.9 The program status registers .................................................................... 2-16
2.10 Additional instructions ............................................................................... 2-23
2.11 Exceptions ................................................................................................ 2-33
Chapter 3 Control Coprocessor CP15
3.1 About control coprocessor CP15 ................................................................ 3-2
3.2 CP15 registers arranged by function .......................................................... 3-4
3.3 Summary of control coprocessor CP15 registers and operations .............. 3-8
3.4 Register descriptions ................................................................................ 3-14
Chapter 4 Unaligned and Mixed-Endian Data Access Support
4.1 About unaligned and mixed-endian support ............................................... 4-2
4.2 Unaligned access support .......................................................................... 4-3
4.3 Unaligned data access specification .......................................................... 4-7
4.4 Operation of unaligned accesses ............................................................. 4-18
4.5 Mixed-endian access support ................................................................... 4-23
4.6 Instructions to reverse bytes in a general-purpose register ...................... 4-27
4.7 Instructions to change the CPSR E bit ..................................................... 4-28
Chapter 5 Program Flow Prediction
5.1 About program flow prediction .................................................................... 5-2
5.2 Branch prediction ........................................................................................ 5-4
5.3 Return stack ............................................................................................... 5-8
5.4 Instruction Memory Barrier (IMB) instruction .............................................. 5-9
5.5 ARM1020T or later IMB implementation .................................................. 5-10
Chapter 6 Memory Management Unit
6.1 About the MMU ........................................................................................... 6-2
6.2 TLB organization ........................................................................................ 6-4
6.3 Memory access sequence .......................................................................... 6-7
6.4 Enabling and disabling the MMU ................................................................ 6-9
6.5 Memory access control ............................................................................. 6-11
6.6 Memory region attributes .......................................................................... 6-15
6.7 Memory attributes and types .................................................................... 6-24
6.8 MMU aborts .............................................................................................. 6-34
6.9 MMU fault checking .................................................................................. 6-36
6.10 Fault status and address .......................................................................... 6-42
6.11 Hardware page table translation ............................................................... 6-45
6.12 MMU descriptors ...................................................................................... 6-53
6.13 MMU software-accessible registers .......................................................... 6-65
6.14 MMU and write buffer ............................................................................... 6-67
Chapter 7 Level One Memory System
7.1 About the level one memory system ........................................................... 7-2
7.2 Cache organization ..................................................................................... 7-3
7.3 Tightly-coupled memory .............................................................................. 7-8
7.4 DMA .......................................................................................................... 7-11
7.5 TCM and cache interactions ..................................................................... 7-13
7.6 Cache debug ............................................................................................. 7-17
7.7 Write buffer ............................................................................................... 7-18
Chapter 8 Level Two Interface
8.1 About the level two interface ....................................................................... 8-2
8.2 Synchronization primitives .......................................................................... 8-7
8.3 AHB-Lite control signals in the ARM1136JF-S processor ......................... 8-10
8.4 Instruction Fetch Interface AHB-Lite transfers .......................................... 8-22
8.5 Data Read Interface AHB-Lite transfers .................................................... 8-26
8.6 Data Write Interface AHB-Lite transfers .................................................... 8-51
8.7 DMA Interface AHB-Lite transfers ............................................................. 8-67
8.8 Peripheral Interface AHB-Lite transfers .................................................... 8-69
8.9 AHB-Lite .................................................................................................... 8-72
Chapter 9 Clocking and Resets
9.1 Clocking ...................................................................................................... 9-2
9.2 Reset ........................................................................................................... 9-7
9.3 Reset modes ............................................................................................... 9-8
Chapter 10 Power Control
10.1 About power control .................................................................................. 10-2
10.2 Power management .................................................................................. 10-3
Chapter 11 Coprocessor Interface
11.1 About the coprocessor interface ............................................................... 11-2
11.2 Coprocessor pipeline ................................................................................ 11-3
11.3 Token queue management ..................................................................... 11-10
11.4 Token queues ......................................................................................... 11-14
11.5 Data transfer ........................................................................................... 11-18
11.6 Operations .............................................................................................. 11-23
11.7 Multiple coprocessors ............................................................................. 11-27
Chapter 12 Vectored Interrupt Controller Port
12.1 About the PL192 Vectored Interrupt Controller ......................................... 12-2
12.2 About the ARM1136JF-S VIC port ............................................................ 12-3
12.3 Timing of the VIC port ............................................................................... 12-5
12.4 Interrupt entry flowchart ............................................................................ 12-8
Chapter 13 Debug
13.1 Debug systems ......................................................................................... 13-2
13.2 About the debug unit ................................................................................ 13-4
13.3 Debug registers ........................................................................................ 13-7
13.4 CP14 registers reset ............................................................................... 13-24
13.5 CP14 debug instructions ........................................................................ 13-25
13.6 Debug events ......................................................................................... 13-28
13.7 Debug exception ..................................................................................... 13-32
13.8 Debug state ............................................................................................ 13-34
13.9 Debug communications channel ............................................................ 13-38
13.10 Debugging in a cached system .............................................................. 13-39
13.11 Debugging in a system with TLBs .......................................................... 13-40
13.12 Monitor debug-mode debugging ............................................................. 13-41
13.13 Halt mode debugging ............................................................................. 13-47
13.14 External signals ...................................................................................... 13-49
Chapter 14 Debug Test Access Port
14.1 Debug Test Access Port and Halt mode .................................................. 14-2
14.2 Synchronizing RealView™ ICE ................................................................ 14-3
14.3 Entering debug state ................................................................................ 14-4
14.4 Exiting debug state ................................................................................... 14-5
14.5 The DBGTAP port and debug registers .................................................... 14-6
14.6 Debug registers ........................................................................................ 14-8
14.7 Using the Debug Test Access Port ......................................................... 14-24
14.8 Debug sequences ................................................................................... 14-34
14.9 Programming debug events ................................................................... 14-48
14.10 Monitor debug-mode debugging ............................................................. 14-50
Chapter 15 Trace Interface Port
15.1 About the ETM interface ........................................................................... 15-2
Chapter 16 Cycle Timings and Interlock Behavior
16.1 About cycle timings and interlock behavior .............................................. 16-3
16.2 Register interlock examples ..................................................................... 16-8
16.3 Data processing instructions .................................................................... 16-9
16.4 QADD, QDADD, QSUB, and QDSUB instructions ................................. 16-12
16.5 ARMv6 media data processing ............................................................... 16-13
16.6 ARMv6 Sum of Absolute Differences (SAD) .......................................... 16-15
16.7 Multiplies ................................................................................................. 16-16
16.8 Branches ................................................................................................ 16-18
16.9 Processor state updating instructions ..................................................... 16-19
16.10 Single load and store instructions ........................................................... 16-20
16.11 Load and store double instructions ......................................................... 16-23
16.12 Load and store multiple instructions ....................................................... 16-25
16.13 RFE and SRS instructions ...................................................................... 16-28
16.14 Synchronization instructions ................................................................... 16-29
16.15 Coprocessor instructions ......................................................................... 16-30
16.16 No operation instruction .......................................................................... 16-31
16.17 SWI, BKPT, Undefined, and Prefetch Aborted instructions .................... 16-32
16.18 Thumb instructions .................................................................................. 16-33
Chapter 17 AC Characteristics
17.1 ARM1136JF-S timing diagrams ................................................................ 17-2
17.2 ARM1136JF-S timing parameters ............................................................. 17-3
Appendix A Signal Descriptions
A.1 Global signals ............................................................................................. A-2
A.2 Static configuration signals ......................................................................... A-3
A.3 Interrupt signals (including VIC interface) ................................................... A-4
A.4 AHB interface signals .................................................................................. A-5
A.5 Coprocessor interface signals ................................................................... A-14
A.6 Debug interface signals (including JTAG) ................................................. A-16
A.7 ETM interface signals ............................................................................... A-17
A.8 Test signals ............................................................................................... A-18
Appendix B Functional changes in the rev1 (r1p0) release
B.1 New instructions .......................................................................................... B-2
B.2 Changes to unaligned access support ........................................................ B-3
B.3 Memory system architecture changes ........................................................ B-4
B.4 Debug changes ........................................................................................... B-7
B.5 VFP changes (ARM1136JF-S only) ............................................................ B-8
B.6 Effects on coprocessor 15 .......................................................................... B-9</P> |
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