经典的状态机设计的资料1

abrahambh

【文件名】:06324@52RD_Designing Safe VHDL State Machines with Synplify.rar
【格　式】:rar
【大　小】:164K
【简　介】:One of the strengths of Synplify is the Finite State Machine compiler.  This is a
powerful feature that not only has the ability to automatically detect state machines in the
source code, and implement them with either sequential, gray, or one-hot encoding.
But also perform a reachability analysis to determine all the states that could possibly be
reached, and optimize away all states and transition logic that can not be reached.
Thus, producing a highly optimal final implementation of the state machine.
In the vast majority of situations this behavior is desirable.  There are occasions,
however, when the removal of unreachable states is not acceptable.  One clear example
is when the final circuit will be subjected to a harsh operating environment, such as
space applications where there may be high levels of radiation.  In the presence of high
levels of radiation, storage elements (flip-flops) have been known to change state due to
alpha particle hits.  If a single bit of a state register were to suddenly change value, the
resulting state may be invalid.  If the invalid states and transition logic had been
removed, the circuit may never get back to a valid state.
By default Synplify will create state machines that are optimized for speed and area.
This application note will use an example state machine design to show the default small
& fast implementation.  It will also demonstrate how to trade-off some of that speed &
area to produce highly reliable state machines using Synplify.

【目　录】:
1.One possible RTL implementation would be
2.Default Implementation
3."Safe" Implementation
4."Exact" Implementation

abrahambh

【文件名】:06324@52RD_状态机设计.rar
【格　式】:rar
【大　小】:113K
【简　介】:The current state of the machine is stored in the
state memory, a set of n flip-flops clocked by a single clock signal (hence “synchronous” state machine). The state vector (also current state, or just state) is the value currently stored by the state memory. The next state of the machine is a function of the state vector and the inputs. Mealy outputs [7]  are a function of the state vector and the inputs  while Moore outputs [8] are a  function of the state  vector only.
【目　录】:
1.0 Introduction
All possible combinations of current state and
2.0 Basic HDL coding
3.0 State assignment
4.0 Coding state transitions
5.0 Outputs
6.0 Inputs
7.0 FSM extract
8.0 Timing constraints
9.0 Synthesis strategies
10.0 Compile results
11.0 Hints, tips, tricks, mysteries
12.0 Acknowledgments
13.0 References
A.0 Appendix

luren123

xie   xie  xie

qinzonghao

没有免费的呀?