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我这边碰到一点问题，请各位高手不吝赐教，芯片是普通AD芯片，SPI传输方式，上升沿有效，现在读不回来数据，07A版本，请帮助看一下，非常感谢。
// Register map
//=============
#define PWR_CONTROL 0x00 // RW Power & conversion control
#define STAGE_CAL_EN 0x01 // RW Ambient compensation control register 0
#define AMB_COMP_CTRL0 0x02 // RW Ambient compensation control register 1
#define AMB_COMP_CTRL1 0x03 // RW Ambient compensation control register 2
#define AMB_COMP_CTRL2 0x04 // RW Ambient compensation control register 3
#define STAGE_LOW_INT_EN 0x05 // RW Interrupt enable register 0
#define STAGE_HIGH_INT_EN 0x06 // RW Interrupt enable register 1
#define STAGE_COMPLETE_INT_EN 0x07 // RW Interrupt enable register 2
#define STAGE_LOW_LIMIT_INT 0x08 // R Low limit interrupt status register 0
#define STAGE_HIGH_LIMIT_INT 0x09 // R High limit interrupt status register 1
#define STAGE_COMPLETE_LIMIT_INT 0x0A // R Interrupt status register 2
#define ADCRESULT_S0 0x0B // R ADC stage 0 result (uncompensated) actually located in SRAM
#define ADCRESULT_S1 0x0C // R ADC stage 1 result (uncompensated) actually located in SRAM
#define ADCRESULT_S2 0x0D // R ADC stage 2 result (uncompensated) actually located in SRAM
#define ADCRESULT_S3 0x0E // R ADC stage 3 result (uncompensated) actually located in SRAM
#define ADCRESULT_S4 0x0F // R ADC stage 4 result (uncompensated) actually located in SRAM
#define ADCRESULT_S5 0x10 // R ADC stage 5 result (uncompensated) actually located in SRAM
#define ADCRESULT_S6 0x11 // R ADC stage 6 result (uncompensated) actually located in SRAM
#define ADCRESULT_S7 0x12 // R ADC stage 7 result (uncompensated) actually located in SRAM
#define ADCRESULT_S8 0x13 // R ADC stage 8 result (uncompensated) actually located in SRAM
#define ADCRESULT_S9 0x14 // R ADC stage 9 result (uncompensated) actually located in SRAM
#define ADCRESULT_S10 0x15 // R ADC stage 10 result (uncompensated) actually located in SRAM
#define ADCRESULT_S11 0x16 // R ADC stage 11 result (uncompensated) actually located in SRAM
#define ADCRESULT_S12 0x16 // R ADC stage 11 result (uncompensated) actually located in SRAM
#define DEVID 0x17 // R I.D. Register
#define THRES_STAT_REG0 0x40 // R Current threshold status register 0
#define THRES_STAT_REG1 0x41 // R Current threshold status register 1
#define PROX_STAT_REG 0x42 // R Current proximity status register 2
// Ram map - these registers are defined as we go along
//=====================================================
#define STAGE0_CONNECTION 0x80
#define STAGE1_CONNECTION 0x88
#define STAGE2_CONNECTION 0x90
#define STAGE3_CONNECTION 0x98
#define STAGE4_CONNECTION 0xA0
#define STAGE5_CONNECTION 0xA8
#define STAGE6_CONNECTION 0xB0
#define STAGE7_CONNECTION 0xB8
#define STAGE8_CONNECTION 0xC0
#define STAGE9_CONNECTION 0xC8
#define STAGE10_CONNECTION 0xD0
#define STAGE11_CONNECTION 0xD8
#define STAGE12_CONNECTION 0xD8
#define STAGE0 0xE0
#define STAGE0_AMBIENT 0xF1
#define STAGE0_MAX_AVG 0xF9
#define STAGE0_UPP_THRES 0xFA
#define STAGE0_MIN_AVG 0x100
#define STAGE0_LWR_THRES 0x101
#define STAGE1 0x104
#define STAGE1_AMBIENT 0x115
#define STAGE1_MAX_AVG 0x11D
#define STAGE1_UPP_THRES 0x11E
#define STAGE1_MIN_AVG 0x124
#define STAGE1_LWR_THRES 0x125
#define STAGE2 0x128
#define STAGE2_AMBIENT 0x139
#define STAGE2_MAX_AVG 0x141
#define STAGE2_UPP_THRES 0x142
#define STAGE2_MIN_AVG 0x148
#define STAGE2_LWR_THRES 0x149
#define STAGE3 0x14C
#define STAGE3_AMBIENT 0x15D
#define STAGE3_MAX_AVG 0x165
#define STAGE3_UPP_THRES 0x166
#define STAGE3_MIN_AVG 0x16C
#define STAGE3_LWR_THRES 0x16D
#define STAGE4 0x170
#define STAGE4_AMBIENT 0x181
#define STAGE4_MAX_AVG 0x189
#define STAGE4_UPP_THRES 0x18A
#define STAGE4_MIN_AVG 0x190
#define STAGE4_LWR_THRES 0x191
#define STAGE5 0x194
#define STAGE5_AMBIENT 0x1A5
#define STAGE5_MAX_AVG 0x1AD
#define STAGE5_UPP_THRES 0x1AE
#define STAGE5_MIN_AVG 0x1B4
#define STAGE5_LWR_THRES 0x1B5
#define STAGE6 0x1B8
#define STAGE6_AMBIENT 0x1C9
#define STAGE6_MAX_AVG 0x1D1
#define STAGE6_UPP_THRES 0x1D2
#define STAGE6_MIN_AVG 0x1D8
#define STAGE6_LWR_THRES 0x1D9
#define STAGE7 0x1DC
#define STAGE7_AMBIENT 0x1ED
#define STAGE7_MAX_AVG 0x1F5
#define STAGE7_UPP_THRES 0x1F6
#define STAGE7_MIN_AVG 0x1FC
#define STAGE7_LWR_THRES 0x1FD
#define STAGE8 0x200
#define STAGE8_AMBIENT 0x211
#define STAGE8_MAX_AVG 0x219
#define STAGE8_UPP_THRES 0x21A
#define STAGE8_MIN_AVG 0x220
#define STAGE8_LWR_THRES 0x221
#define STAGE9 0x224
#define STAGE9_AMBIENT 0x234
#define STAGE9_MAX_AVG 0x23D
#define STAGE9_UPP_THRES 0x23E
#define STAGE9_MIN_AVG 0x244
#define STAGE9_LWR_THRES 0x245
#define STAGE10 0x248
#define STAGE10_AMBIENT 0x259
#define STAGE10_MAX_AVG 0x261
#define STAGE10_UPP_THRES 0x262
#define STAGE10_MIN_AVG 0x268
#define STAGE10_LWR_THRES 0x269
#define STAGE11 0x26C
#define STAGE11_AMBIENT 0x27D
#define STAGE11_MAX_AVG 0x285
#define STAGE11_UPP_THRES 0x286
#define STAGE11_MIN_AVG 0x28C
#define STAGE11_LWR_THRES 0x28D
#define STAGE12 0x26C
#define STAGE12_AMBIENT 0x27D
#define STAGE12_MAX_AVG 0x285
#define STAGE12_UPP_THRES 0x286
#define STAGE12_MIN_AVG 0x28C
#define STAGE12_LWR_THRES 0x28D
///////////////////////////////////////////////////////////////////////////////////////////
#define SPI_AD7147_CLK_PIN 1
#define SPI_AD7147_DIN_PIN 2
#define SPI_AD7147_DOUT_PIN 3
#define SPI_AD7147_CS_PIN 26
#define SPI_POWER 35
#define SET_AD7147_CLK_HIGH() (GPIO_WriteIO(1,SPI_AD7147_CLK_PIN))
#define SET_AD7147_CLK_LOW() (GPIO_WriteIO(0,SPI_AD7147_CLK_PIN))
#define SET_AD7147_DATA_HIGH() GPIO_WriteIO(1,SPI_AD7147_DIN_PIN)
#define SET_AD7147_DATA_LOW() GPIO_WriteIO(0,SPI_AD7147_DIN_PIN)
#define GET_AD7147_DATA_BIT() GPIO_ReadIO(SPI_AD7147_DOUT_PIN)
//#define GET_BUSY_BIT() GPIO_ReadIO(SPI_BUSY_PIN)
#define SET_CS_HIGH() GPIO_WriteIO(1,SPI_AD7147_CS_PIN)
#define SET_CS_LOW() GPIO_WriteIO(0,SPI_AD7147_CS_PIN)
///////////////////////////////////////////////////////////////////////////////////////////
typedef struct structTWOBYTES
{
unsigned char high;
unsigned char low;
} struct_TWOBYTES;
typedef union unionADcommand
{
unsigned int intCmd;
struct_TWOBYTES byteCmd;
} union_ADcommand;
unsigned int AD7147Registers[24]; //[0...23 inc]=1st set of registers [0...23 inc]
void spiADDelay(void)
{
unsigned char x;
for(x = 35;x > 0;x--);
}
/////////////////////////////////////////////////
/*write 1*/
void serial_AD7147_write_bit_high(void)
{
SET_AD7147_DATA_HIGH(); /* ---- */
SET_AD7147_CLK_LOW(); /* _-_ */
serial_delay();
SET_AD7147_CLK_HIGH();
serial_delay();
SET_AD7147_CLK_LOW();
}
/*write 0*/
void serial_AD7147_write_bit_low(void)
{
SET_AD7147_DATA_LOW(); /* ____ */
SET_AD7147_CLK_LOW(); /* _-_ */
serial_delay();
SET_AD7147_CLK_HIGH();
serial_delay();
SET_AD7147_CLK_LOW();
}
/*read*/
kal_uint16 serial_AD7147_read_data(void)
{
kal_uint16 data=0;
kal_int16 i;
kal_uint32 savedMask;
kal_uint32 retry=0;
//savedMask = SaveAndSetIRQMask();
SET_AD7147_CLK_LOW();
SET_AD7147_CLK_HIGH();
#if 1
while(retry<50)
{
retry++;
}
#else
while(GET_BUSY_BIT())
{
SET_AD7147_CLK_LOW();
SET_AD7147_CLK_HIGH();
retry++;
if(retry>1000000)/*give up the read. controller may be broken*/
return 0;
};
#endif
for(i=11;i>=0;i--)
{
//SET_CLK_LOW();
//serial_delay();
SET_AD7147_CLK_HIGH();
serial_delay();
if(GET_AD7147_DATA_BIT())
data |= (1<<i);
SET_AD7147_CLK_LOW();
serial_delay();
}
data&=0x3fff;
return data;
}
void serial_AD7147_write_data(kal_uint8 data)
{
kal_int16 i;
for (i=7;i>=0;i--)
{ /* data bit 7~0 */
if (data & (1<<i))
{
serial_AD7147_write_bit_high();
}
else
{
serial_AD7147_write_bit_low();
}
}
SET_AD7147_DATA_LOW();
}
void sendrcvSPI(kal_uint16 data)
{
//SET_CS_LOW();
//spiADDelay();
serial_AD7147_write_data(data);
//SET_CS_HIGH();
}
////////////////////////////////////////////////
void WriteToAD7147 (unsigned int addrCS, unsigned int RegisterAddress, unsigned char NumberOfRegisters, unsigned int *DataBuffer, unsigned int OffsetInBuffer)
{
unsigned int ControlValue;
unsigned int ValueToWrite;
unsigned char RegisterIndex;
union_ADcommand val;
SET_CS_LOW();
//Create the 16-bit header
ControlValue = 0xE000 | (RegisterAddress & 0x03FF);
val.intCmd = ControlValue;
sendrcvSPI(val.byteCmd.high); // send command
sendrcvSPI(val.byteCmd.low); // send command
//And then the data
for (RegisterIndex=0; RegisterIndex<NumberOfRegisters; RegisterIndex++)
{
ValueToWrite= *(DataBuffer+RegisterIndex+OffsetInBuffer);
val.intCmd = ValueToWrite;
sendrcvSPI(val.byteCmd.high); // send write command
sendrcvSPI(val.byteCmd.low); // send write command
}
SET_CS_HIGH();
}
kal_uint16 RecSPIData(kal_uint8 data)
{
recdata=serial_AD7147_read_data();
return recdata;
}
void ReadFromAD7147 (unsigned int addrCS, unsigned int RegisterAddress, unsigned char NumberOfRegisters, unsigned int *DataBuffer, unsigned int OffsetInBuffer)
{
unsigned int ControlValue;
unsigned char RegisterIndex;
union_ADcommand val;
SET_CS_LOW();
spiADDelay();
//Create the 16-bit header
ControlValue = 0xE400 | (RegisterAddress & 0x03FF);
val.intCmd = ControlValue;
sendrcvSPI(val.byteCmd.high); // send command
sendrcvSPI(val.byteCmd.low); // send command
spiADDelay();
spiADDelay();
//And then the data
for (RegisterIndex=0; RegisterIndex<NumberOfRegisters; RegisterIndex++)
{
//////////////////////////////////////////////////////////////////
val.byteCmd.high = RecSPIData(0xCC); // send write command
val.byteCmd.low = RecSPIData(0xCC); // send write command
///////////////////////////////////////////////
AD7147Registers[RegisterIndex] = val.intCmd;
}
SET_CS_HIGH();
}
unsigned int spiReadADWord(unsigned int addr, unsigned char length )
{
ReadFromAD7147(addr, ADCRESULT_S0, length, AD7147Registers, ADCRESULT_S0);
return 0;
}
void initializeAD7147 (unsigned int addCS)
{
unsigned char i;
unsigned int StageBuffer[8];
for ( i=0; i<24; i++)
{
AD7147Registers = 0;
}
//==========================================
//============ Bank 2 Registers ============
//==========================================
//=================================
//= Stage 0 - CIN0(+) - Button S1 =
//=================================
StageBuffer[0]=0xFFFE; //Register 0x80
StageBuffer[1]=0x1FFF; //Register 0x81
StageBuffer[2]=0x1600; //Register 0x82
StageBuffer[3]=0x2626; //Register 0x83
StageBuffer[4]=0x4E20; //Register 0x84
StageBuffer[5]=0x4E20; //Register 0x85
StageBuffer[6]=0x4E20; //Register 0x86
StageBuffer[7]=0x4E20; //Register 0x87
WriteToAD7147(addCS, STAGE0_CONNECTION, 8, StageBuffer, 0);
//=================================
//= Stage 1 - CIN1(+) - Button S2 =
//=================================
StageBuffer[0]=0xFFFB; //Register 0x88
StageBuffer[1]=0x1FFF; //Register 0x89
StageBuffer[2]=0x1700; //Register 0x8A
StageBuffer[3]=0x2626; //Register 0x8B
StageBuffer[4]=0x4E20; //Register 0x8C
StageBuffer[5]=0x4E20; //Register 0x8D
StageBuffer[6]=0x4E20; //Register 0x8E
StageBuffer[7]=0x4E20; //Register 0x8F
WriteToAD7147(addCS, STAGE1_CONNECTION, 8, StageBuffer, 0);
//=================================
//= Stage 2 - CIN2(+) - Button S3 =
//=================================
StageBuffer[0]=0xFFEF; //Register 0x90
StageBuffer[1]=0x1FFF; //Register 0x91
StageBuffer[2]=0x1700; //Register 0x92
StageBuffer[3]=0x2626; //Register 0x93
StageBuffer[4]=0x4E20; //Register 0x94
StageBuffer[5]=0x4E20; //Register 0x95
StageBuffer[6]=0x4E20; //Register 0x96
StageBuffer[7]=0x4E20; //Register 0x97
WriteToAD7147(addCS, STAGE2_CONNECTION, 8, StageBuffer, 0);
//=================================
//= Stage 3 - CIN3(+) - Button S4 =
//=================================
StageBuffer[0]=0xFFBF; //Register 0x98
StageBuffer[1]=0x1FFF; //Register 0x99
StageBuffer[2]=0x1700; //Register 0x9A
StageBuffer[3]=0x2626; //Register 0x9B
StageBuffer[4]=0x4E20; //Register 0x9C
StageBuffer[5]=0x4E20; //Register 0x9D
StageBuffer[6]=0x4E20; //Register 0x9E
StageBuffer[7]=0x4E20; //Register 0x9F
WriteToAD7147(addCS, STAGE3_CONNECTION, 8, StageBuffer, 0);
//==================================
//= Stage 4 - CIN4(+) - Button S5 =
//==================================
StageBuffer[0]=0xFEFF; //Register 0xA0
StageBuffer[1]=0x1FFF; //Register 0xA1
StageBuffer[2]=0x1700; //Register 0xA2
StageBuffer[3]=0x2626; //Register 0xA3
StageBuffer[4]=0x4E20; //Register 0xA4
StageBuffer[5]=0x4E20; //Register 0xA5
StageBuffer[6]=0x4E20; //Register 0xA6
StageBuffer[7]=0x4E20; //Register 0xA7
WriteToAD7147(addCS, STAGE4_CONNECTION, 8, StageBuffer, 0);
//=================================
//= Stage 5 - CIN5(+) - Button S6 =
//=================================
StageBuffer[0]=0xFBFF; //Register 0xA8
StageBuffer[1]=0x1FFF; //Register 0xA9
StageBuffer[2]=0x1800; //Register 0xAA
StageBuffer[3]=0x2626; //Register 0xAB
StageBuffer[4]=0x4E20; //Register 0xAC
StageBuffer[5]=0x4E20; //Register 0xAD
StageBuffer[6]=0x4E20; //Register 0xAE
StageBuffer[7]=0x4E20; //Register 0xAF
WriteToAD7147(addCS, STAGE5_CONNECTION, 8, StageBuffer, 0);
//=================================
//= Stage 6 - CIN6(+) - Button S7 =
//=================================
StageBuffer[0]=0xEFFF; //Register 0xB0
StageBuffer[1]=0x1FFF; //Register 0xB1
StageBuffer[2]=0x1800; //Register 0xB2
StageBuffer[3]=0x2626; //Register 0xB3
StageBuffer[4]=0x4E20; //Register 0xB4
StageBuffer[5]=0x4E20; //Register 0xB5
StageBuffer[6]=0x4E20; //Register 0xB6
StageBuffer[7]=0x4E20; //Register 0xB7
WriteToAD7147(addCS, STAGE6_CONNECTION, 8, StageBuffer, 0);
//=================================
//= Stage 7 - CIN7(+) - Button S8 =
//=================================
StageBuffer[0]=0xFFFF; //Register 0xB8
StageBuffer[1]=0x1FFE; //Register 0xB9
StageBuffer[2]=0x1800; //Register 0xBA
StageBuffer[3]=0x2626; //Register 0xBB
StageBuffer[4]=0x4E20; //Register 0xBC
StageBuffer[5]=0x4E20; //Register 0xBD
StageBuffer[6]=0x4E20; //Register 0xBE
StageBuffer[7]=0x4E20; //Register 0xBF
WriteToAD7147(addCS, STAGE7_CONNECTION, 8, StageBuffer, 0);
//=================================
//= Stage 8 - CIN8(+) - Button S9 =
//=================================
StageBuffer[0]=0xFFFF; //Register 0xC0
StageBuffer[1]=0x1FFB; //Register 0xC1
StageBuffer[2]=0x1700; //Register 0xC2
StageBuffer[3]=0x2626; //Register 0xC3
StageBuffer[4]=0x4E20; //Register 0xC4
StageBuffer[5]=0x4E20; //Register 0xC5
StageBuffer[6]=0x4E20; //Register 0xC6
StageBuffer[7]=0x4E20; //Register 0xC7
WriteToAD7147(addCS, STAGE8_CONNECTION, 8, StageBuffer, 0);
//==================================
//= Stage 9 - CIN9(+) - Button S10 =
//==================================
StageBuffer[0]=0xFFFF; //Register 0xC8
StageBuffer[1]=0x1FEF; //Register 0xC9
StageBuffer[2]=0x1800; //Register 0xCA
StageBuffer[3]=0x2626; //Register 0xCB
StageBuffer[4]=0x4E20; //Register 0xCC
StageBuffer[5]=0x4E20; //Register 0xCD
StageBuffer[6]=0x4E20; //Register 0xCE
StageBuffer[7]=0x4E20; //Register 0xCF
WriteToAD7147(addCS, STAGE9_CONNECTION, 8, StageBuffer, 0);
//====================================
//= Stage 10 - CIN10(+) - Button S11 =
//====================================
StageBuffer[0]=0xFFFF; //Register 0xD0
StageBuffer[1]=0x1FBF; //Register 0xD1
StageBuffer[2]=0x1800; //Register 0xD2
StageBuffer[3]=0x2626; //Register 0xD3
StageBuffer[4]=0x4E20; //Register 0xD4
StageBuffer[5]=0x4E20; //Register 0xD5
StageBuffer[6]=0x4E20; //Register 0xD6
StageBuffer[7]=0x4E20; //Register 0xD7
WriteToAD7147(addCS, STAGE10_CONNECTION, 8, StageBuffer, 0);
//====================================
//= Stage 11 - CIN11(+) - Button S12 =
//====================================
StageBuffer[0]=0xFFFF; //Register 0xD8
StageBuffer[1]=0x1EFF; //Register 0xD9
StageBuffer[2]=0x1700; //Register 0xDA
StageBuffer[3]=0x2626; //Register 0xDB
StageBuffer[4]=0x4E20; //Register 0xDC
StageBuffer[5]=0x4E20; //Register 0xDD
StageBuffer[6]=0x4E20; //Register 0xDE
StageBuffer[7]=0x4E20; //Register 0xDF
WriteToAD7147(addCS, STAGE11_CONNECTION, 8, StageBuffer, 0);
//==========================================
//============ Bank 1 Registers ============
//==========================================
//Initialisation of the first register bank but not the STAGE_CAL_EN
AD7147Registers[PWR_CONTROL]=0x03B0; //Register 0x01
WriteToAD7147(addCS,PWR_CONTROL, 1, AD7147Registers, PWR_CONTROL);
AD7147Registers[AMB_COMP_CTRL0]=0x3230; //Register 0x02
AD7147Registers[AMB_COMP_CTRL1]=0x0419; //Register 0x03
AD7147Registers[AMB_COMP_CTRL2]=0x0832; //Register 0x04
AD7147Registers[STAGE_LOW_INT_EN]=0x0000; //Register 0x05
AD7147Registers[STAGE_HIGH_INT_EN]=0x0000; //Register 0x06
AD7147Registers[STAGE_COMPLETE_INT_EN]=0x0001; //Register 0x07
WriteToAD7147(addCS,AMB_COMP_CTRL0, 6, AD7147Registers, AMB_COMP_CTRL0);
//Enable data path for all sequences
AD7147Registers[STAGE_CAL_EN]=0x0FFF; //Register 0x00
WriteToAD7147(addCS, STAGE_CAL_EN, 1, AD7147Registers, STAGE_CAL_EN);
}
/////////////////////////////////////////////////////////////////////////////////////////////////////////
void Ad7147_Init()
{
GPIO_ModeSetup(SPI_POWER,0x0);
GPIO_InitIO(1,SPI_POWER);
GPIO_WriteIO(1,SPI_POWER);
GPIO_ModeSetup(SPI_AD7147_DIN_PIN, 0x0);
GPIO_ModeSetup(SPI_AD7147_CLK_PIN, 0x0);
GPIO_ModeSetup(SPI_AD7147_DOUT_PIN, 0x0);
GPIO_ModeSetup(SPI_AD7147_CS_PIN, 0x0);
GPIO_InitIO(OUTPUT,SPI_AD7147_DIN_PIN); //OUTPUT 1，INPUT 0
GPIO_InitIO(OUTPUT,SPI_AD7147_CLK_PIN);
GPIO_InitIO(INPUT,SPI_AD7147_DOUT_PIN);
GPIO_InitIO(OUTPUT,SPI_AD7147_CS_PIN);
GPIO_WriteIO(1,SPI_AD7147_CS_PIN);
} |
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IP卡
狗仔卡
发表于 2009-12-27 18:21:08
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