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[资料] ESD in Silicon Integrated Circuits (2nd Ed.)

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发表于 2009-10-6 08:48:36 | 显示全部楼层 |阅读模式
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【文件名】:09106@52RD_ESD in Silicon Integrated Circuits (2nd Ed.).rar
【格 式】:rar
【大 小】:3791K
【简 介】:
【目 录】:




ESD in silicon integrated circuits 2nd.
Introduction 1
1.1 Background 1
1.2 The ESD Problem 3
1.3 Protecting Against ESD 4
1.4 Outline of the Book 4

2 ESD Phenomenon 8
2.1 Introduction 8
2.2 Electrostatic Voltage 9
2.3 Discharge 11
2.4 ESD Stress Models 12

3 Test Methods 17
3.1 Introduction 17
3.2 Human Body Model (HBM) 18
3.3 Machine Model (MM) 27
3.4 Charged Device Model (CDM) 28
3.5 Socket Device Model (SDM) 40
3.6 Metrology, Calibration, Verification 42
3.7 Transmission Line Pulsing (TLP) 47
3.8 Failure Criteria 58
3.9 Summary 60

4 Physics and Operation of ESD Protection Circuit Elements 68
4.1 Introduction 68
4.2 Resistors 68
4.3 Diodes 70
4.4 Transistor Operation 77
4.5 Transistor Operation under ESD Conditions 85
4.6 Electrothermal Effects 95
4.7 SCR Operation 98
4.8 Conclusion 101

5 ESD Protection Circuit Design Concepts and Strategy 105
5.1 The Qualities of Good ESD Protection 106
5.2 ESD Protection Design Methods 109
5.3 Selecting an ESD Strategy 123
5.4 Summary 124

6 Design and Layout Requirements 126
6.1 Introduction 126
6.2 Thick Field Device 127
6.3 nMOS Transistors (FPDs) 132
6.4 Gate-Coupled nMOS (GCNMOS) 138
6.5 Gate Driven nMOS (GDNMOS) 149
6.6 SCR Protection Device 150
6.7 ESD Protection Design Synthesis 155
6.8 Total Input Protection 164
6.9 ESD Protection Using Diode-Based Devices 172
6.10 Power Supply Clamps 176
6.11 Bipolar and BiCMOS Protection Circuits 179
6.12 Summary 183

7 Advanced Protection Design 188
7.1 Introduction 188
7.2 PNP-Driven nMOS (PDNMOS) 188
7.3 Substrate Triggered nMOS (STNMOS) 189
7.4 nMOS Triggered nMOS (NTNMOS) 192
7.5 ESD for Mixed-Voltage I/O 200
7.6 CDM Protection 214
7.7 SOI Technology 215
7.8 High-Voltage Transistors 216
7.9 BiCMOS Protection 218
7.10 RF Designs 219
7.11 General I/O Protection Schemes 220
7.12 Design/Layout Errors 221
7.13 Summary 223

8 Failure Modes, Reliability Issues, and Case Studies 228
8.1 Introduction 228
8.2 Failure Mode Analysis 229
8.3 Reliability and Performance Considerations 238
8.4 Advanced CMOS Input Protection 239
8.5 Optimizing the Input Protection Scheme 242
8.6 Designs for Special Applications 249
8.7 Process Effects on Input Protection Design 253
8.8 Total IC Chip Protection 255
8.9 Power Bus Protection 256
8.10 Internal Chip ESD Damage 258
8.11 Stress Dependent ESD Behavior 263
8.12 Failure Mode Case Studies 267
8.13 Summary 271

9 Influence of Processing on ESD 282
9.1 Introduction 282
9.2 High Current Behavior 284
9.3 Cross Section of a MOS Transistor 287
9.4 Drain-Source Implant Effects 288
9.5 p-Well Effects 293
9.6 n-Well Effects 294
9.7 Epitaxial Layers and Substrates 295
9.8 Gate Oxides 298
9.9 Silicides 300
9.10 Contacts 304
9.11 Interconnect and Metalization 305
9.12 Gate Length Dependencies 306
9.13 Silicon-on-Insulator (SOI) 310
9.14 Bipolar Transistors 312
9.15 Diodes 314
9.16 Resistors 315
9.17 Reliability Trade-Offs 316
9.18 Summary 317

10 Device Modeling of High Current Effects 326
10.1 Introduction 326
10.2 The Physics of ESD Damage 327
10.3 Thermal (“Second”) Breakdown 330
10.4 Analytical Models Using the Heat Equation 335
10.5 Electrothermal Device Simulations 339
10.6 Conclusion 344

11 Circuit Simulation Basics, Approaches, and Applications 350
11.1 Introduction 350
11.2 Modeling the MOSFET 351
11.3 Modeling Bipolar Junction Transistors 367
11.4 Modeling Diffusion Resistors 371
11.5 Modeling Protection Diodes 375
11.6 Simulation of Protection Circuits 376
11.7 Electrothermal Circuit Simulations 382
11.8 Conclusion 385
12 Conclusion 394
12.1 Long-Term Relevance of ESD In ICs 394
12.2 State-of-the-Art for ESD Protection 395
12.3 Current Limitations 396
12.4 Future Issues 398

[此贴子已经被作者于2009-10-6 10:49:30编辑过]
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