vhdl参考手册

fpga22892

一本不错的VHDL参考手册，共249页，E文，SYNOPSYS出品。
文章目录如下
FPGA Express
VHDL Reference Manual
Table of Contents
1 Using FPGA Express with VHDL
  Hardware Description Languages 1-2
  Typical Uses for HDLs 1-2
  Advantages of HDLs. 1-2
  About VHDL 1-3
  FPGA Express Design Process 1-5
  Using FPGA Express to Compile a VHDL Design 1-6
  Design Methodology 1-7
2 Description Styles
  Design Hierarchy 2-2
  Data Types 2-2
  Design Constraints 2-3
  Register Selection. 2-3
  Asynchronous Designs. 2-3
  Language Constructs 2-4
3 Describing Designs
  VHDL Entities 3-1
  VHDL Constructs. 3-4
  Entities. 3-4
  Architectures 3-5
  Configurations. 3-7
  Processes 3-7
  Subprograms 3-9
  Packages 3-10
  Using a Package 3-10
  Package Structure. 3-11
  Package Declarations 3-11
  Package Bodies 3-12
  Defining Designs 3-13
  Entity Specifications 3-13
  Entity Generic Specifications. 3-14
  Entity Port Specifications. 3-14
  Entity Architectures. 3-15
  Entity Configurations 3-18
  Subprograms 3-19
  Subprogram Declarations. 3-20
  Subprogram Bodies 3-21
  Subprogram Overloading 3-22
  Operator Overloading. 3-23
  Type Declarations 3-24
  Subtype Declarations. 3-24
  Constant Declarations 3-24
  Signal Declarations 3-25
  Resolution Functions. 3-25
  Variable Declarations 3-28
  Structural Design 3-29
  Using Hardware Components 3-30
  Component Declaration. 3-30
  Sources of Components 3-31
  Consistency of Component Ports 3-31
  Component Instantiation Statement 3-32
  Mapping Generic Values 3-32
  Mapping Port Connections. 3-33
  Technology-Independent Component Instantiation 3-34
4 Data Types
  Enumeration Types 4-2
  Enumeration Overloading 4-3
  Enumeration Encoding 4-3
  Enumeration Encoding Values 4-5
  Integer Types 4-6
  Array Types 4-7
  Constrained Array 4-7
  Unconstrained Array 4-8
  Array Attributes. 4-9
  Record Types 4-10
  Predefined VHDL Data Types 4-11
  BOOLEAN Data Type 4-12
  BIT Data Type. 4-13
  CHARACTER Data Type. 4-13
  INTEGER Data Type 4-13
  NATURAL Data Type 4-13
  POSITIVE Data Type 4-13
  STRING Data Type. 4-14
  BIT_VECTOR Data Type. 4-14
  Unsupported Data Types 4-14
  Physical Types. 4-14
  Floating Point Types 4-14
  Access Types. 4-14
  File Types 4-15
  SYNOPSYS Data Types 4-15
  Subtypes 4-15
5 Expressions
  Operators 5-2
  Logical Operators 5-3
  Relational Operators 5-5
  Adding Operators 5-7
  Unary (Sign) Operators 5-9
  Multiplying Operators 5-9
  Miscellaneous Arithmetic Operators. 5-12
  Operands. 5-13
  Operand Bit Width 5-14
  Computable Operands 5-14
  Literals. 5-17
  Numeric Literals. 5-17
  Character Literals 5-17
  Enumeration Literals 5-17
  String Literals. 5-18
  Identifiers 5-19
  Indexed Names 5-20
  Slice Names. 5-21
  Limitations on Null Slices 5-22
  Limitations on Noncomputable Slices 5-23
  Records and Fields 5-23
  Aggregates. 5-24
  Attributes. 5-26
  Function Calls 5-27
  Qualified Expressions 5-28
6 Sequential Statements
  Assignment Statements 6-2
  Assignment Targets. 6-3
  Simple Name Targets 6-3
  Indexed Name Targets 6-4
  Slice Targets 6-5
  Field Targets 6-6
  Aggregate Targets 6-7
  Variable Assignment Statement 6-8
  Signal Assignment Statement. 6-9
  Variable Assignment 6-9
  Signal Assignment. 6-9
  if Statements 6-10
  Evaluating condition 6-11
  Using the if Statement to Imply Registers and Latches 6-12
  case Statement 6-12
  Using Different Expression Types 6-13
  Invalid case Statements 6-14
  loop Statements 6-15
  loop Statement. 6-16
  while. loop Statement 6-17
  for. loop Statement 6-17
  next Statements 6-20
  exit Statements 6-22
  Subprograms. 6-23
  Subprogram Calls 6-24
  Procedure Calls 6-25
  Function Calls 6-27
  return Statements 6-28
  Mapping Subprograms to Components (Entities). 6-29
  wait Statements 6-34
  Inferring Synchronous Logic 6-34
  Combinational vs. Sequential Processes 6-38
  null Statements 6-40
7 Concurrent Statements
  process Statements 7-2
  Combinational Process Example. 7-3
  Sequential Process Example 7-4
  Driving Signals 7-6
  block Statements 7-7
  Concurrent Procedure Calls 7-9
  Concurrent Signal Assignments 7-11
  Conditional Signal Assignment. 7-12
  Selected Signal Assignment 7-13
  Component Instantiations. 7-15
  generate Statements 7-17
  for. generate Statement 7-17
  if generate Statement 7-20
8 Register and Three-State Inference
  Register Inference 8-1
  Using Register Inference. 8-2
  Describing Clocked Signals 8-2
  wait versus if Statements 8-4
  Recommended Use of Register Inference Capabilities 8-4
  Restrictions on Register Capabilities 8-6
  Delays in Registers 8-7
  Describing Latches 8-7
  Automatic Latch Inferencing 8-8
  Restrictions on Latch Inference Capabilities 8-9
  Example—Design with Two-Phase Clocks 8-10
  Describing Flip-Flops 8-11
  Flip-Flop with Asynchronous Reset. 8-11
  Example—Synchronous Design with Asynchronous Reset 8-13
  Attributes. 8-15
  async_set_reset. 8-15
  Latch with Asynchronous Set or Clear Inputs 8-15
  sync_set_reset 8-16
  Flip-Flop with Synchronous Reset Input 8-16
  async_set_reset_local 8-17
  sync_set_reset_local. 8-19
  async_set_reset_local_all 8-21
  sync_set_reset_local_all. 8-23
  one_hot 8-25
  one_cold 8-27
  FPGA Express Latch and Flip-Flop Inference 8-29
  Efficient Use of Registers 8-30
  Example—Using Synchronous and Asynchronous Processes. 8-32
  Three-State Inference 8-35
  Assigning the Value Z. 8-36
  Latched Three-State Variables 8-37
9 FPGA Express Directives
  Notation for FPGA Express Directives 9-2
  FPGA Express Directives. 9-2
  Translation Stop and Start Directives 9-3
  Resolution Function Directives. 9-5
  Component Implication Directives 9-5
10 Synopsys Packages
  std_logic_1164 Package. 10-1
  std_logic_arith Package 10-2
  Using the Package 10-3
  Modifying the Package 10-3
  Data Types. 10-4
  UNSIGNED 10-5
  SIGNED. 10-5
  Conversion Functions 10-6
  Arithmetic Functions. 10-8
  Comparison Functions. 10-11
  Shift Functions 10-13
  Multiplication Using Shifts 10-14
  ENUM_ENCODING Attribute. 10-14
  pragma built_in 10-15
  Two-Argument Logic Functions 10-15
  One-Argument Logic Functions 10-16
  Type Conversion 10-17
  translate_off Directive. 10-18
  std_logic_misc Package 10-18
11 VHDL Constructs
  VHDL Construct Support. 11-1
  Design Units 11-2
  Data Types. 11-3
  Declarations. 11-4
  Specifications 11-5
  Names 11-5
  Operators 11-6
  Operands and Expressions 11-7
  Sequential Statements 11-8
  Concurrent Statements 11-9
  Predefined Language Environment 11-9
  VHDL Reserved Words 11-11


【文件名】:06312@52RD_VHDL参考手册.pdf
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