<P><b>SPI features (Motolora design)</b></P><UL><LI>full duplex, four-wrie synchronous transfers <LI>programmable clock polarity and phase <LI>4-16bits </LI></UL><P><b>Synchronous serial interface features(SSI)(Texas Instrumnets )</b></P><UL><LI>full-duplex, four-wire synchronous transfer <LI>transmit data pin trstateable when not transmitting <LI>4-16bit</LI></UL><P> For SPI frame formats, the serial frame (SSPESSOUT) pin is active LOW, and is asserted (plled down) during the entire transmission of the frame.</P><P> For SSI. SSPESSOUT pin is pulsed for one serial clokc period starting at its rising edge, prior to the transmission of each trame. For this frame format, both the SSP and the off-chip slave drive their ouput data on the rising edge of SSPCLKOUT, and latch data from the other device on the falling edge.</P>[br]<p align=right><font color=red>+3 RD币</font></p>