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(Lectures)
RF/RFIC Circuit Design
Richard Chi-Hsi Li
李 缉 熙
2008
Part 1 Design Technologies and Schemes
Lecture 1 Different Methodology between RF and Digital
Circuit Design 1 hour
(0.17 days)
1.1 Controversy
1.1.1 Impedance Matching
1.1.2 Key Parameter
1.1.3 Circuit Testing and Main Test Equipments
1.2 Differences of Digital and RF Blocks in a Communication System
1.2.1 Impedance
1.2.2 Current drain
1.2.3 Location
1.3 Conclusion
1.4 Notes for High Speed Digital Circuit Design
Lectue 2 Voltage and Power Transportation 2 hours
(0.33 days)
2.1 Voltage Delivered from a Source to a Load
2.1.1 General Expression of Voltage Delivered from a Source to a Load
2.1.2 Additional Jitter or Distortion in a Digital Circuit Block
2.2 Power Delivered from a Source to a Load
2.2.1 General Expression of Power Delivered from a Source to a Load
2.2.2 Power Instability
2.2.3 Additional Power Loss
2.2.4 Additional Distortion
2.2.5 Additional Interference
2.3 Impedance Conjugate Matching
2.3.1 Maximization of Power Transportation
2.3.2 Power Transportation without Phase Shift
2.3.3 Impedance Matching Network
2.3.4 Necessity of Impedance Matching
2.4 Additional Effects of Impedance Matching
2.4.1 Voltage Pumped Up by Means of Impedance Matching
2.4.2 Power Measurement
Appendixes
2A.1 VSWR and Other Reflection and Transmission Coefficients
2A.2 Relationships between Power (dBm), Voltage (V), and Power (Watt)
Lecture 3 Impedance Matching in Narrow Band Case 4 hours
(0.67 days)
3.1 Introduction
3.2 Impedance Matching by Means of Return Loss Adjustment
3.2.1 Return Loss Circles on Smith Chart
3.2.2 Relationship between Return Loss and Impedance Matching
3.2.3 Implementation of an Impedance Matching Network
3.3 Impedance Matching Network Built by One Part
3.3.2 One Part Inserted into Impedance Matching Network in Series
3.3.3 One Part Inserted into Impedance Matching Network in Parallel
3.4 Impedance Matching Network Built by Two Parts
3.4.1 Regions in the Smith Chart
3.4.2 Value of Parts
3.4.3 Selection of Topology
3.5 Impedance Matching Network Built by Three Parts
3.5.1 “Π” and “T” Types
3.5.2 Recommended Topologies
3.6 Impedance Matching when ZS or ZL is not 50 Ω
3.7 Parts in an Impedance Matching Network
Appendixes
3A.1 Fundamentals of the Smith Chart
3A.2 Formula for a Two Parts Impedance Matching Network
3A.3 Topology Restrictions of the Two Parts Impedance Matching Network
3A.4 Topology Restrictions of the Three Parts Impedance Matching Network
3A.5 Conversion between “Π” and “T” type Matching Networks
3A.6 Possible “Π” and “T” Impedance Matching Networks
Lecture 4 Impedance Matching in Wide Band Case 3 hours
(0.5 days)
4.1 Appearance of Narrow and Wide Band Return Loss on Smith Chart
4.2 Impedance Variation due to Insertion of One Part per Arm
or per Branch
4.2.1 An Inductor Inserted into Impedance Matching Network in Series
4.2.2 A Capacitor Inserted into Impedance Matching Network in Series
4.2.3 An Inductor Inserted into Impedance Matching Network in Parallel
4.2.4 A Capacitor Inserted into Impedance Matching Network in Parallel
4.3 Impedance Variation due to Insertion of Two Parts per Arm
or per Branch
4.3.1 Two Parts Connected in Series to Form One Arm
4.3.2 Two Parts Connected in Parallel to Form One Branch
4.4 Impedance Matching in IQ Modulator Design for UWB System
in UWB System
4.4.1 Gilbert Cell in IQ Modulator
4.4.2 Impedances of Gilbert Cell
4.4.3 Impedance Matching for LO, RF and IF Ports Ignoring Bandwidth
4.4.4 Wide Bandwidth Required in UWB(Ultra Wide Band) System
4.4.5 Basic Idea to Expand the Bandwidth
4.4.6 Example#1: Impedance Matching in IQ Modulator Design
for Group#1 in UWB System
4.4.7 Example#2: Impedance Matching in IQ Modulator Design
for Group#3+Group#6 in UWB System
4.5 Discussion of Wide-band Impedance Matching Network
4.5.1 Impedance Matching for Gate of MOSFET device
4.5.2 Impedance Matching for Drain of MOSFET device
Lecture 5 Impedance and Gain of a Raw Device 2 hours
(0.33 days)
5.1 Introduction
5.2 Miller Effect
5.3 Small Signal Model of Bipolar Transistor
5.4 Bipolar Transistor with CE (Common Emitter) Configuration
5.4.1 Open-circuited Voltage Gain Av,CE of a CE Device
5.4.2 Short-circuited Current Gain βCE and Frequency Response of a CE Device
5.4.3 Primary Input and Output Impedances of a CE Device
5.4.4 Miller Effect on a CE device
5.4.5 Emitter Degeneration
5.5 Bipolar Transistor with CB (Common Base) Configuration
5.5.1. Open-circuited Voltage Gain Av,CB of a CB Device
5.5.2. Short-circuited Current Gain βCB and Frequency Response of a CB Device
5.5.3. Input and Output Impedances of a CB Device
5.6 Bipolar Transistor with CC (Common Collector) Configuration
5.6.1 Open-circuited Voltage Gain Av,CC of a CC Device
5.6.2 Short-circuited Current Gain βCC and Frequency Response of a CC Device
5.6.3 Input and Output Impedances of a CC Device
5.7 Small Signal Model of MOSFET Transistor
5.8 Similarity between Bipolar and MOSFET Transistor
5.8.1 Simplified Model of CS device
5.8.2 Simplified Model of CG device
5.8.3 Simplified Model of CD device
5.9 MOSFET Transistor with CS (Common Source) Configuration
5.9.1 Open-circuited Voltage Gain Av,CS of a CS Device
5.9.2 Short-circuited Current Gain βCS and Frequency Response of a CS Device
5.9.3 Input and Output Impedances of a CS Device
5.9.4 Source Degeneration
5.10 MOSFET Transistor with CG (Common Gate) Configuration
5.10.1 Open-circuited Voltage Gain Av,CG of a CG Device
5.10.2 Short-circuited Current Gain βCG and Frequency Response of a CG Device
5.10.3 Input and Output Impedances of a CG Device
5.11 MOSFET Transistor with CD (Common Drain) Configuration
5.11.1 Open-circuited Voltage Gain Av,CD of a CD Device
5.11.2 Short-circuited Current Gain βCD and Frequency Response of a CD Device
5.11.3 Input and Output Impedances of a CD Device
5.12 Comparison of Bipolar and MOSFET Transistor in Various
Configurations
Lecture 6 Impedance Measurement 1 hours
(0.17 days)
6.1 Introduction
6.2 Scale and Vector Voltage Measurement
6.2.1 Voltage Measurement by Oscilloscope
6.2.2 Voltage Measurement by Vector-Voltmeter
6.3 Direct Impedance Measurement by Network Analyzer
6.3.1 Direction of Impedance Measurement
6.3.2 Advantages of Measuring S Parameters
6.3.3 Theoretical Background of Impedance Measurement by S Parameters
6.3.4 S Parameter Measurement by Vector-Voltmeter
6.3.5 Calibration of Network Analyzer
6.4 Alternative Impedance Measurement by Network Analyzer
6.4.1 Accuracy of Smith Chart
6.4.2 Low and High Impedance Measurement
6.5 Impedance measurement by Assistance of Circulator
Appendixes
6A.1 Relationship Between the Impedance in Series and in Parallel
Lecture 7 Grounding 4 hours
(0.67 days)
7.1 Implications of Grounding
7.2 Possible Grounding Problems Hidden in a Schematic
7.3 Imperfect or Inappropriate Grounding Examples
7.3.1 Inappropriate Selection of Bypass Capacitor
7.3.2 Imperfect Grounding
7.3.3 Improper Connection
7.4 “Zero” Capacitor
7.4.1 What is a “Zero” Capacitor?
7.4.2 Selection of the “Zero” Capacitor
7.4.3 Bandwidth of the “Zero” Capacitor
7.4.4 Combined Effect of Multiple “Zero” Capacitors
7.4.5 Chip Inductor is a Good Assistant
7.4.6 “Zero” Capacitor in RFIC Design
7.5 Quarter Wavelength of Micro Strip Line
7.5.1 A Runner is a Part in RF Circuitry
7.5.2 Why the Quarter Wavelength is so Important?
7.5.3 The Magic of the Open-circuited Quarter-Wavelength Micro Strip Line
7.5.4 Testing for Width of a Micro Strip Line with a Specific
Characteristic Impedance
7.5.5 Testing for the Quarter Wavelength
Appendixes
7A.1 Characterizing a Chip Capacitor and Chip Inductor by Means of S21 Testing
Lecture 8 Equipotentiality and Current Coupling
on the Ground Surface 2 hours
(0.33 days)
8.1 Equipotentiality on the Grounded Surface
8.1.1 Equipotentiality on the Grounded Surface of a RF cable
8.1.2 Equipotentiality on the Grounded Surface of a PCB
8.1.3 Possible Problems of a Large Test PCB
8.1.4 Coercing Grounding
8.1.5 Testing for Equipotentiality
8.2 Forward and Return Current Coupling
8.3.1 “Indifferent Assumption” and the “Great Ignore”
8.3.2 Reduction of Current Coupling on a PCB
8.3.3 Reduction of Current Coupling in a IC Die
8.3.4 Reduction of Current Coupling between Multiple RF Blocks
8.3.5 A Plausible System Assembly
8.3 PCB and IC Chip with Multi Metallic Layers
Appendixes
8A.1 Primary Considerations of a PCB
Lecture 9 RFIC (Radio Frequency Integrated Circuit) and
SOC (System on Chip) 4 hours
(0.67 days)
9.1 Interference and Isolation
9.1.1 Existence of Interference in Circuitry
9.1.2 Definition and Measurement of Isolation
9.1.3 Main Path of Interference in a RF Module
9.1.4 Main Path of Interference in a IC Die
9.2 Shielding for a RF Module by a Metallic Shielding Box
9.3 Strong Desirability to Develop RFIC
9.4 Interference Going Along IC Substrate Path
9.4.1. Experimentation
9.4.2. Trench
9.4.3. Guard Ring
9.5 Solution for Interference Coming from the Sky
9.6 Common Grounding Rules for RF Module and RFIC Design
9.6.1. Grounding of Circuit-branches or Blocks in Parallel
9.6.2. DC Power Supply to Circuit-branches or Blocks in Parallel
9.7 Bottlenecks in RFIC
9.7.1 Low Q Inductor and Possible Solution
9.7.2 “Zero” Capacitors
9.7.3 Bonding Wires
9.8 Prospect of SOC
9.9 What is Next?
Appendixes
9A.1 Notes about RFIC layout
9A.2 Calculation of Quarter Wavelength
Lecture 10 Manufacturability of Product Design 2 hours
(0.33 days)
10.1 Introduction
10.2 Implication of 6σ Design
10.2.1 6σ and Yield Rate
10.2.2 6σ Design for a Circuit Block
10.3 Approaching 6σ Design
10.3.1 By Changing Parts’ 6σ Value
10.3.2 By Replacing a Single Part with Multiple Parts
10.4 Monte Carlo Analysis
10.4.1 A BPF (Band Pass Filter)
10.4.2 Simulation with Monte Carlo Analysis
10.4.3 Sensitivity of Parts on the Parameter of Performance
Appendixes
10A.1 Fundamentals of Random Process
10A.2 Index Cp, Cpk and Other Parameters Applied in 6σ Design
10A.3 Table of the Normal Distribution
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