Documentation Of Digital Electronic Systems With VHDL

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【文件名】:06221@52RD_Documentation Of Digital Electronic Systems With VHDL.rar
【格　式】:rar
【大　小】:1816K
【简　介】:
1. This handbook is approved for use by all Departments and Agencies of the Department of Defense (DoD).
2. This handbook is for guidance only. This handbook cannot be cited as a requirement. If it is, the contractor
does not have to comply.
3. This handbook was developed to provide guidance to Department of Defense personnel who are writing requests
for proposals for military digital electronic systems, DoD contractors who are developing very high-speed
integrated circuit (VHSIC) hardware description language (VHDL) models for the Government, and DoD engineers,
scientists, and management or independent validation and verification contractors who are evaluating or reviewing
models delivered to the Government. It documents the state of the art and existing technologies for VHDL
model development. Addressed in the handbook are which VHDL models are required to be delivered with a contract,
which VHDL models should be developed during the different stages of the lifetime of a system, and how
VHDL models can be structured to be consistent with modeling standards.
4. This handbook was developed under the auspices of the US Army Materiel Command’s Engineering Design
Handbook Program, which is under the direction of the US Army Industrial Engineering Activity. Research Triangle
Institute (RTI) was the prime contractor for this handbook under Contract No. DAAA09-86-D-0009. The handbook
was authored by Dr. Geoffrey A. Frank and edited by Ray C. Anderson of RTI. Development of this handbook was
guided by a technical working group that included Mr. Gerald T. Michael, US Army Research Laboratory, chairman;
Dr. John W. Hines, US Air Force Wright Laboratory; Mr. J. P. Letellier, US Naval Research Laboratory; and
Mr. Michael A. Frye, US Department of Defense, Defense Logistics Agency.
5. Beneficial comments (recommendations, additions, deletions) and any pertinent data that may be of use in improving
this document should be addressed to Defense Supply Center Columbus, ATTN: Director-VA, 3990 East
Broad Street, Columbus, OH 43216-5000, by using the Standardization Document Improvement Proposal (DD
Form 1426) appearing at the end of this document or by letter.
【目　录】:
iii
CONTENTS
FOREWORD ...............................................ii
LIST OF ILLUSTRATIONS ......................ix
LIST OF TABLES ......................................xi
LIST OF ABBREVIATIONS AND ACRONYMS...................................................................................................................xii
CHAPTER 1
INTRODUCTION
1-1 PURPOSE ..................................... 1-1
1-2 SCOPE .......................................... 1-1
1-3 INTENDED AUDIENCE ............. 1-1
1-4 HISTORY, PURPOSE, AND SCOPE OF VHDL ....................................................................................................... 1-2
1-4.1 HISTORY OF VHDL ..... 1-2
1-4.2 THE PURPOSE OF VHDL ............................................................................................................................ 1-2
1-4.3 THE SCOPE OF VHDL .. 1-3
1-5 RELATED INDUSTRY STANDARDS ...................................................................................................................... 1-3
1-6 OVERVIEW ................................. 1-3
REFERENCES ....................................... 1-4
BIBLIOGRAPHY .................................. 1-5
CHAPTER 2
HARDWARE DESCRIPTION CONCEPTS
2-1 INTRODUCTION ........................ 2-1
2-2 LEVELS OF ABSTRACTION IN MODELS OF DIGITAL ELECTRONIC SYSTEMS .......................................... 2-2
2-2.1 OVERVIEW .................... 2-2
2-2.2 NETWORK MODELS .... 2-3
2-2.2.1 Performance Models . 2-3
2-2.2.2 Interface models ....... 2-3
2-2.3 ALGORITHMIC MODELS ............................................................................................................................ 2-4
2-2.4 INSTRUCTION SET ARCHITECTURE MODELS ..................................................................................... 2-4
2-2.5 REGISTER-TRANSFER MODELS ............................................................................................................... 2-4
2-2.6 GATE-LEVEL MODELS ............................................................................................................................... 2-4
2-2.7 USES OF ABSTRACTION AND HIERARCHICAL DECOMPOSITION IN THE DESIGN
PROCESS ........................ 2-5
2-3 BEHAVIORAL DESCRIPTIONS OF HARDWARE DESIGNS ............................................................................... 2-5
2-3.1 THE PURPOSE OF BEHAVIORAL DESCRIPTIONS ................................................................................ 2-5
2-3.2 THE USE OF HIERARCHY IN BEHAVIORAL DESCRIPTIONS ............................................................. 2-6
2-3.3 EXAMPLE OF A BEHAVIORAL DESCRIPTION ...................................................................................... 2-7
2-4 STRUCTURAL DESCRIPTIONS OF HARDWARE DESIGNS ............................................................................... 2-12
2-4.1 THE PURPOSE OF STRUCTURAL DESCRIPTIONS ................................................................................ 2-12
2-4.2 THE USE OF HIERARCHY IN STRUCTURAL DESCRIPTIONS ............................................................. 2-13
2-4.2.1 Hierarchical Decomposition Based on Physical Elements ....................................................................... 2-13
2-4.2.2 Leaf Modules in a Hierarchical Structural Description ............................................................................ 2-14
2-4.3 EXAMPLES OF STRUCTURAL DESCRIPTIONS ..................................................................................... 2-14
2-4.3.1 Algorithmic-Level Structural Description ................................................................................................ 2-14
2-4.3.2 Register-Transfer-Level Structural Description ....................................................................................... 2-20
2-5 MIXED ABSTRACTION MODELS ........................................................................................................................... 2-22
2-5.1 THE PURPOSE OF MIXED LEVEL OF ABSTRACTION MODELS ........................................................ 2-22
2-5.2 DESIGNING MODULES FOR MIXED ABSTRACTION MODELS .......................................................... 2-22
2-5.3 AN EXAMPLE OF A MIXED LEVEL OF ABSTRACTION MODEL ....................................................... 2-23
REFERENCES ....................................... 2-23
BIBLIOGRAPHY .................................. 2-24
MIL-HDBK-62
iv
CHAPTER 3
VHDL CONCEPTS
3-1 INTRODUCTION ........................ 3-1
3-2 BASIC VHDL CONCEPTS ......... 3-1
3-2.1 VHDL DESIGN ENTITIES ............................................................................................................................ 3-1
3-2.1.1 Entity Interfaces ........ 3-2
3-2.1.2 Architecture Bodies .. 3-3
3-2.2 THE VHDL CONCEPT OF TIME ................................................................................................................. 3-4
3-2.3 SIGNALS ........................ 3-4
3-2.3.1 Signal Assignment Statements ................................................................................................................. 3-4
3-2.3.2 Resolution Functions  3-5
3-3 VHDL SUPPORT FOR BEHAVIORAL DESIGN ..................................................................................................... 3-6
3-3.1 PROCESSES ................... 3-6
3-3.2 WAIT STATEMENTS .... 3-7
3-3.3 A BEHAVIORAL DESIGN EXAMPLE ........................................................................................................ 3-7
3-4 VHDL SUPPORT FOR STRUCTURAL DESIGN ..................................................................................................... 3-8
3-4.1 STRUCTURAL ARCHITECTURE BODIES ................................................................................................ 3-8
3-4.2 COMPONENTS .............. 3-8
3-4.2.1 Component Declarations .......................................................................................................................... 3-8
3-4.2.2 Component Instantiations and Interconnections ....................................................................................... 3-9
3-4.3 A STRUCTURAL DESIGN EXAMPLE ....................................................................................................... 3-9
3-5 VHDL SUPPORT FOR DATA ABSTRACTION ....................................................................................................... 3-10
3-5.1 USER-DEFINED TYPES ............................................................................................................................... 3-11
3-5.2 TYPE CONVERSION FUNCTIONS ............................................................................................................. 3-11
3-5.3 OVERLOADED OPERATORS ..................................................................................................................... 3-12
3-6 VHDL SUPPORT FOR ANNOTATING MODELS ................................................................................................... 3-12
3-6.1 ATTRIBUTES ................. 3-12
3-6.2 GENERIC CONSTANTS ............................................................................................................................... 3-13
3-6.3 PHYSICAL TYPES ........ 3-13
3-7 ERROR HANDLING WITH VHDL ............................................................................................................................ 3-14
3-7.1 ASSERTION STATEMENTS ........................................................................................................................ 3-14
3-7.2 HANDLING SIGNAL ERROR STATES ...................................................................................................... 3-15
3-8 VHDL SUPPORT FOR SHARING AND REUSE ...................................................................................................... 3-15
3-8.1 VHDL DESIGN LIBRARIES ......................................................................................................................... 3-16
3-8.1.1 Declaring and Using Libraries .................................................................................................................. 3-16
3-8.1.2 Constructing Libraries .............................................................................................................................. 3-19
3-8.2 VHDL PACKAGES ........ 3-20
3-8.2.1 Constructing VHDL Packages .................................................................................................................. 3-20
3-8.2.2 Declaring and Using Packages ................................................................................................................. 3-20
3-8.3 CONFIGURATION SPECIFICATIONS AND DECLARATIONS .............................................................. 3-20
3-8.3.1 Constructing Configuration Specifications and Declarations .................................................................. 3-21
3-8.3.2 Using Configuration Specifications and Declarations .............................................................................. 3-22
REFERENCES........................................ 3-24
BIBLIOGRAPHY ................................... 3-24
CHAPTER 4
DoD REQUIREMENTS FOR THE USE OF VHDL
4-1 INTRODUCTION ........................ 4-1
4-2 MIL-HDBK-454 GUIDELINES FOR THE USE OF VHDL ...................................................................................... 4-1
4-2.1 DOCUMENTATION OF ASICs DEVELOPED FOR THE GOVERNMENT WITH VHDL ..................... 4-1
4-2.2 DOCUMENTATION OF QUALIFIED DIGITAL INTEGRATED CIRCUITS WITH VHDL ................... 4-2
4-2.3 THE LIBRARY OF VHDL DESCRIPTIONS OF STANDARD DIGITAL PARTS .................................... 4-2
4-2.4 TEST BENCH REQUIREMENTS FOR VHDL DESCRIPTIONS................................................................ 4-2
4-3 OVERVIEW OF THE VHDL DATA ITEM DESCRIPTION .................................................................................... 4-2
4-3.1 ENTITY INTERFACE REQUIREMENTS .................................................................................................... 4-3
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MIL-HDBK-62
4-3.1.1 Entity Names ............ 4-3
4-3.1.2 Input and Output Definitions .................................................................................................................... 4-3
4-3.2 BEHAVIORAL DESCRIPTIONS .................................................................................................................. 4-4
4-3.2.1 Functional Decomposition ........................................................................................................................ 4-4
4-3.2.2 Timing Descriptions . 4-5
4-3.3 STRUCTURAL DESCRIPTIONS .................................................................................................................. 4-5
4-3.3.1 Acceptable Primitive Elements ................................................................................................................ 4-5
4-3.3.2 Testability Requirements .......................................................................................................................... 4-5
4-3.4 TEST BENCH REQUIREMENTS ................................................................................................................. 4-6
4-3.4.1 Test Bench Functions ............................................................................................................................... 4-6
4-3.4.2 Test Bench Relationships to Design Modules .......................................................................................... 4-7
4-3.5 ERROR MESSAGES ...... 4-7
4-3.6 DOCUMENTATION FORMAT .................................................................................................................... 4-7
4-3.7 REQUIRED ANNOTATIONS OF VHDL MODULES ................................................................................. 4-8
4-3.8 AN EXAMPLE OF A TAILORED DID ........................................................................................................ 4-8
REFERENCES........................................ 4-8
BIBLIOGRAPHY ................................... 4-9

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CHAPTER 5
CONSTRUCTION OF BEHAVIORAL VHDL MODELS
5-1 INTRODUCTION ........................ 5-1
5-2 CREATION OF VHDL BEHAVIORAL MODELS .................................................................................................... 5-1
5-2.1 CONSTRUCTING PERFORMANCE MODELS .......................................................................................... 5-1
5-2.1.2 Modeling Timing in Performance- and Algorithmic-Level Behavioral Models ...................................... 5-2
5-2.1.3 Example of a Statistics Package and Its Use ............................................................................................ 5-2
5-2.2 CONSTRUCTING ALGORITHMIC MODELS ............................................................................................ 5-6
5-2.2.1 Modeling Algorithms With VHDL Processes .......................................................................................... 5-7
5-2.2.2 An Example of an Algorithmic Model ..................................................................................................... 5-7
5-2.3 CONSTRUCTING INSTRUCTION-SET-ARCHITECTURE-LEVEL MODELS ....................................... 5-11
5-2.3.1 Modeling Processors . 5-11
5-2.3.2 Modeling Memory .... 5-17
5-2.3.3 Modeling Busses and Bus Controllers ...................................................................................................... 5-18
5-2.4 CONSTRUCTING REGISTER-TRANSFER-LEVEL MODELS ................................................................. 5-19
5-2.4.1 Synthesis of Designs From RTL Models ................................................................................................. 5-19
5-2.4.2 An Example of a VHDL Register-Transfer-Level Model ........................................................................ 5-20
5-3 VHDL DID SIMULATION REQUIREMENTS FOR BEHAVIORAL MODELS .................................................... 5-21
5-3.1 CORRECT FUNCTIONAL RESPONSE TO STIMULI ............................................................................... 5-21
5-3.2 SIMULATION TIMING . 5-21
5-3.3 ERROR HANDLING ...... 5-21
5-4 TIMING IN BEHAVIORAL MODELS ...................................................................................................................... 5-22
5-4.1 TIMING SHELLS ........... 5-22
5-4.2 CLOCK RATES .............. 5-24
5-4.3 CRITICAL PATH DELAY TIMES ................................................................................................................ 5-24
5-4.4 BEST-CASE, WORST-CASE, AND NOMINAL DELAYS ......................................................................... 5-24
5-4.5 PARAMETERIZED DELAY MODELS ........................................................................................................ 5-24
5-4.6 TIMING DEFINITION PACKAGE ............................................................................................................... 5-26
5-4.7 TIMING THROUGH FILE INPUT ................................................................................................................ 5-31
5-4.8 MODELING ASYNCHRONOUS TIMING .................................................................................................. 5-32
5-4.9 MODELING SYNCHRONOUS TIMING ..................................................................................................... 5-33
5-5 ANNOTATION OF BEHAVIORAL MODELS .......................................................................................................... 5-36
5-5.1 DESCRIPTION OF FUNCTION .................................................................................................................... 5-36
5-5.2 DESCRIPTION OF RESTRICTIONS ............................................................................................................ 5-36
5-5.3 MODELING APPROACH ............................................................................................................................. 5-36
5-5.4 REVISION HISTORY .... 5-37
5-5.5 BACK ANNOTATION OF TIMING INFORMATION ................................................................................ 5-37
MIL-HDBK-62
vi
5-6 USE OF STRUCTURAL HIERARCHY IN BEHAVIORAL MODELS .................................................................... 5-37
REFERENCES ....................................... 5-38
BIBLIOGRAPHY .................................. 5-38
CHAPTER 6
CONSTRUCTION OF STRUCTURAL VHDL MODELS
6-1 INTRODUCTION ........................ 6-1
6-2 CREATION OF STRUCTURAL VHDL MODELS ................................................................................................... 6-1
6-2.1 TRANSLATION OF SCHEMATIC CAPTURE MODELS .......................................................................... 6-1
6-2.2 SYNTHESIS OF STRUCTURAL MODELS FROM REGISTER-TRANSFER-LEVEL MODELS ........... 6-2
6-2.3 SYNTHESIS OF STRUCTURAL MODELS FROM FINITE STATE MACHINES ................................... 6-2
6-2.4 ENHANCEMENT OF GATE-LEVEL MODELS WITH GENERATED STRUCTURE ............................. 6-2
6-3 VHDL DID ORGANIZATIONAL REQUIREMENTS FOR STRUCTURAL MODELS ......................................... 6-3
6-3.1 HIERARCHICAL ORGANIZATION OF STRUCTURAL MODELS ......................................................... 6-3
6-3.2 ALLOWABLE LEAF-LEVEL MODULES ................................................................................................... 6-4
6-3.2.1 Government-Approved Models ................................................................................................................ 6-4
6-3.2.2 Modules With Stimulus-Response Behavior ............................................................................................ 6-4
6-3.2.3 Modules Without Detailed Designs .......................................................................................................... 6-4
6-3.3 VHDL DID ANNOTATION REQUIREMENTS FOR STRUCTURAL MODELS ..................................... 6-5
6-3.3.1 Physical View Requirements .................................................................................................................... 6-6
6-3.3.2 Electrical View Requirements .................................................................................................................. 6-6
6-3.3.3 Timing View Requirements ...................................................................................................................... 6-7
6-4 VHDL DID SIMULATION REQUIREMENTS FOR STRUCTURAL MODELS .................................................... 6-9
6-4.1 SUPPORT FOR LOGIC-LEVEL FAULT MODELING ............................................................................... 6-9
6-4.2 SUPPORT FOR TEST VECTOR GENERATION ........................................................................................ 6-10
6-5 TIMING SPECIFICATIONS FOR STRUCTURAL MODELS .................................................................................. 6-10
6-6 BACK ANNOTATION OF STRUCTURAL MODELS ............................................................................................. 6-11
6-6.1 BACK ANNOTATION OF TIMING INFORMATION ................................................................................ 6-11
6-6.2 BACK ANNOTATION OF LAYOUT INFORMATION .............................................................................. 6-12
6-6.3 BACK ANNOTATION OF TESTABILITY INFORMATION ..................................................................... 6-12
REFERENCES ....................................... 6-12
BIBLIOGRAPHY .................................. 6-13
CHAPTER 7
PREPARATION OF VHDL MODELS FOR SIMULATION
7-1 INTRODUCTION ........................ 7-1
7-2 INTEROPERABILITY OF MODELS ......................................................................................................................... 7-1
7-2.1 USE OF STANDARD SIGNAL DATA TYPES ............................................................................................ 7-2
7-2.2 TYPE CONVERSION FOR DIFFERENT SIGNAL DATA TYPES ............................................................ 7-2
7-2.3 INTEROPERABILITY OF TIMING MODELS ............................................................................................ 7-3
7-2.4 PORTABILITY REQUIREMENTS FOR INTEROPERABLE VHDL MODELS ....................................... 7-3
7-3 TEST BENCH DEVELOPMENT  7-3
7-3.1 WAVES ........................... 7-4
7-3.1.1 Standard WAVES Packages ..................................................................................................................... 7-7
7-3.1.2 Local WAVES Packages .......................................................................................................................... 7-8
7-3.1.3 WAVES Test Suites . 7-8
7-3.2 DOCUMENTATION OF TEST BENCHES .................................................................................................. 7-10
7-4 TEST VECTOR DEVELOPMENT ............................................................................................................................. 7-10
7-4.1 BEHAVIOR TESTS ........ 7-10
7-4.2 PROPAGATION DELAY TESTS ................................................................................................................. 7-11
7-4.3 ERROR CONDITION TESTS ........................................................................................................................ 7-11
7-4.3.1 Invalid Operating Condition Tests ........................................................................................................... 7-12
7-4.3.2 Invalid Input State Tests ........................................................................................................................... 7-12
7-4.3.3 Timing Constraint Violation Tests ........................................................................................................... 7-12
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MIL-HDBK-62
7-4.4 INTEROPERABILITY TESTS ...................................................................................................................... 7-13
7-4.5 ORGANIZATION AND DOCUMENTATION OF TEST VECTORS ......................................................... 7-13
7-5 USE OF CONFIGURATION DECLARATIONS TO INSTANTIATE THE TEST BENCH
FOR A MODEL ........................... 7-14
7-5.1 SELECTION OF ALTERNATIVE DESIGN LIBRARIES ....................................................................... 7-14
7-5.2 SELECTION OF ALTERNATIVE ARCHITECTURES ........................................................................... 7-15
7-5.3 BINDING OF GENERICS .......................................................................................................................... 7-15
7-5.4 PORT MAPPING ........ 7-15
7-6 DEFINITION OF SIMULATOR OPTIONS ................................................................................................................ 7-15
7-6.1 CONTROL OVER ENVIRONMENTAL PARAMETERS ........................................................................... 7-16
7-6.2 SELECTION OF DELAY TYPES ................................................................................................................. 7-16
7-6.3 CONTROL OVER EXECUTION OF ASSERTIONS ................................................................................... 7-16
7-6.4 CONTROL OVER PROPAGATION OF UNKNOWN SIGNAL STATES ................................................. 7-16
REFERENCES ....................................... 7-17
BIBLIOGRAPHY .................................. 7-17

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CHAPTER 8
MODELING TESTABILITY WITH VHDL MODELS
8-1 INTRODUCTION ........................ 8-1
8-2 PURPOSE AND SCOPE OF DESIGN FOR TESTABILITY ..................................................................................... 8-1
8-3 TESTABILITY DESIGN ISSUES ............................................................................................................................... 8-1
8-3.1 TEST STRATEGIES AND TECHNIQUES FOR MAINTENANCE AND FAULT TOLERANCE ........... 8-2
8-3.2 TESTABILITY MEASURES ......................................................................................................................... 8-3
8-3.3 TEST STRUCTURE BOUNDARIES ............................................................................................................ 8-4
8-3.4 TEST COMPONENTS AND INTERFACES ................................................................................................ 8-6
8-4 MODELING TESTABILITY USING VHDL BEHAVIORAL MODELS ................................................................. 8-6
8-4.1 EVALUATING TEST STRATEGIES ........................................................................................................... 8-6
8-4.2 MODELING TEST INTERFACES IN VHDL ............................................................................................... 8-7
8-4.3 MODELING TEST CONTROLLER FUNCTIONS ...................................................................................... 8-7
8-4.4 EVALUATION OF TEST COMMUNICATION AND STORAGE REQUIREMENTS FOR BIT ............. 8-7
8-5 MODELING TESTABILITY USING VHDL STRUCTURAL MODELS ................................................................. 8-7
8-5.1 DESCRIPTION OF TEST CIRCUITRY GENERATED FROM STRUCTURAL INFORMATION .......... 8-7
8-5.2 SUPPORT FOR FAULT DICTIONARY GENERATION ............................................................................ 8-8
8-5.3 SUPPORT FOR AUTOMATIC TEST GENERATION ................................................................................ 8-8
8-5.4 SUPPORT FOR COVERAGE ANALYSIS ................................................................................................... 8-8
8-5.5 SUPPORT FOR TEST TIME COMPUTATION ........................................................................................... 8-8
8-6 ANNOTATION OF VHDL MODELS WITH TESTABILITY INFORMATION ...................................................... 8-8
8-6.1 ANNOTATION OF STRUCTURAL MODELS TO IDENTIFY LRUs ........................................................ 8-8
8-6.2 ANNOTATION OF STRUCTURAL MODELS TO IDENTIFY FCRs ........................................................ 8-9
8-6.3 BACK ANNOTATION WITH COVERAGE INFORMATION ................................................................... 8-9
REFERENCES ....................................... 8-9
BIBLIOGRAPHY .................................. 8-10
CHAPTER 9
PREPARATION OF VHDL MODELS FOR DELIVERY TO THE DoD
9-1 INTRODUCTION ........................ 9-1
9-2 FILES TO BE INCLUDED IN DELIVERY TAPE ..................................................................................................... 9-2
9-2.1 LIST OF FILES ............... 9-2
9-2.2 DID OVERVIEW FILE .. 9-2
9-2.3 VHDL ANALYSIS ORDER SPECIFICATION ............................................................................................ 9-2
9-2.4 GOVERNMENT-APPROVED LEAF MODULE VHDL DESCRIPTIONS ................................................ 9-2
9-2.5 REVISED VHDL MODULE LIST ................................................................................................................ 9-3
9-2.6 ORIGINAL VHDL MODULE LIST .............................................................................................................. 9-3
9-2.7 TEST BENCH CORRELATION LIST .......................................................................................................... 9-3
9-2.8 AUXILIARY INFORMATION FILES .......................................................................................................... 9-4
9-2.9 VHDL DESIGN UNIT FILES ........................................................................................................................ 9-4
MIL-HDBK-62
9-3 FILE NAMING CONVENTIONS ............................................................................................................................... 9-5
9-3.1 NAMING VHDL DESIGN UNIT FILES ....................................................................................................... 9-5
9-3.2 NAMING AUXILIARY FILES ...................................................................................................................... 9-6
9-4 SUGGESTED CODING CONVENTIONS FOR VHDL MODELS ........................................................................... 9-6
9-4.1 DESIGN ENTITY NAMING CONVENTIONS............................................................................................. 9-6
9-4.2 PORT-NAMING CONVENTIONS ................................................................................................................ 9-7
9-4.3 SIGNAL-NAMING CONVENTIONS ........................................................................................................... 9-7
9-4.4 PROCESS AND SUBPROGRAM NAMING CONVENTIONS ................................................................... 9-7
9-4.5 COMMENTING CONVENTIONS FOR VHDL ........................................................................................... 9-7
9-4.5.1 Files .......................... 9-7
9-4.5.2 Packages ................... 9-7
9-4.5.3 Entity Interfaces ........ 9-7
9-4.5.4 Architecture Bodies .. 9-8
9-4.5.5 Configuration Declarations ....................................................................................................................... 9-8
9-4.5.6 Internal Comments ... 9-8
REFERENCES ....................................... 9-8
BIBLIOGRAPHY .................................. 9-8
APPENDIX A .........................................A-1
APPENDIX B .........................................B-1
GLOSSARY............................................G-1
INDEX ..................................................... I-1
SUBJECT TERM (KEY WORD) LISTING ........................................................................................................................ST-1