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请教各位大虾，我在ALTERA开发板上写了一段代码，如下。当我移植到ACTEL上时，发现没有正常收到qmem,qmemm的返回值。请教问题的根本原因。
我的MSN：sky-teng@hotmail.com
library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity fxer is
port (
unout:in std_logic;
sndunout:out std_logic;
unin:in std_logic;
sndunin:out std_logic;
wprocess:in std_logic;
sndwprocess:out std_logic;
--unknow1:in std_logic;
--unknow2:in std_logic;
--sndunknow1:out std_logic;
--sndunknow2:out std_logic;
addr:in std_logic_vector(3 downto 0);
sndaddr:out std_logic_vector(3 downto 0);
djust:in std_logic;
snddjust:out std_logic;
data: inout std_logic_vector(7 downto 0);
snddata: inout std_logic_vector(7 downto 0);
enable: in std_logic;
sndable: out std_logic;
databus:out std_logic_vector(7 downto 0);
P530_A0A1:inout std_logic;
P530_WR:inout std_logic;
P530_CLR:inout std_logic;
P530_0_LDAC:inout std_logic;
P530_1_LDAC:inout std_logic;
P530_0_CS:inout std_logic;
P530_1_CS:inout std_logic;
P530_0_ROFS:inout std_logic;
P530_1_ROFS:inout std_logic
-- ext_ret: in std_logic
);
attribute syn_noclockbuf : Boolean;
attribute syn_noclockbuf of unin:signal is true;
--attribute syn_noclockbuf : Boolean;
--attribute syn_noclockbuf of unout:signal is true;
end fxer;
architecture www of fxer is
type states is (s0,s1,s2,s3,s4,s5,s6,s7,s8);
signal curr_st:states;
signal bus_sel:bit_vector(3 downto 0);
--signal InitoutA0:bit;
--signal InitoutA1:bit;
signal I1:std_logic;
signal I2:std_logic;
signal I3:std_logic;
signal I4:std_logic;
signal I5:std_logic;
signal I6:std_logic;
signal I7:std_logic;
signal I8:std_logic;
signal channel1L_realdata:std_logic_vector(7 downto 0);
signal channel1H_realdata:std_logic_vector(7 downto 0);
signal channel2L_realdata:std_logic_vector(7 downto 0);
signal channel2H_realdata:std_logic_vector(7 downto 0);
signal cp_data:std_logic_vector(7 downto 0);
signal qmem:std_logic_vector(7 downto 0);
signal qmemm:std_logic_vector(7 downto 0);
signal r_flag:std_logic_vector(7 downto 0);
signal read_Counter:integer range 0 to 63;
signal Counter:integer range 0 to 24;
signal Counter_LDAC0:integer range 0 to 25;
signal Counter_LDAC1:integer range 0 to 25;
begin
sndunout<=unout;
sndunin<=unin;
sndwprocess<=wprocess;
snddjust<=djust;
sndaddr<=addr-2 when enable='0' else addr;
sndable<=enable;
--sndunknow1<=unknow1;
--sndunknow2<=unknow2;
P530_CLR<='1';
P530_0_ROFS<='1';------------for 0 to +10V.
P530_1_ROFS<='1';------------for 0 to +10V.
--r_flag<="11111111";
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
snddata<=cp_data when bus_sel="0010" else
data when bus_sel="1000" else "ZZZZZZZZ";
-- "11111111" when bus_sel="0000" else
data<=cp_data when bus_sel="0001" else
"10000111" when bus_sel="0000" else
--"11111111" when bus_sel="0101" else ------------------------------------------
snddata when bus_sel="0111" else
-- "11111111" when bus_sel="0111" else
r_flag when bus_sel="0011" else
qmem when bus_sel="0100" else
qmemm when bus_sel="0110" else "ZZZZZZZZ";
cp_data<=snddata when bus_sel="0001" else
data when bus_sel="0010" else "ZZZZZZZZ";
bus_sel<="0000" when curr_st=s0 else
"0001" when curr_st=s1 else
"0010" when curr_st=s2 else
"0011" when curr_st=s3 else
"0100" when curr_st=s4 else
"0101" when curr_st=s5 else
"0110" when curr_st=s6 else
"0111" when curr_st=s7 else
"1000" when curr_st=s8 else
"1001";
------------------------------------------------------------------
------------------------------------------------------------------
plan_rcounter: process(unout,enable,addr,wprocess,djust,unin,read_Counter)
begin
if(unin'event and unin='0') then
if(wprocess='1' and unout='1' and enable='0' and djust='1' and addr(3 downto 0)="0000" and read_Counter<63) then
read_Counter<=read_Counter+1;
end if;
end if;
end process plan_rcounter;
--------------------------------------------------------------------
----------------------------------------------------------------------
plan_counter: process(unout,enable,addr,wprocess,djust,Counter,unin)
begin
if(Counter=24) then
Counter<=0;
elsif(unin'event and unin='0' and unout='0' and enable='0' and wprocess='1' and addr(3 downto 0)="0001" and djust='0' )then
Counter<=Counter+1;
end if;
end process plan_counter;
------------------------------------------------------------------
------------------------------------------------------------------
plan_I1: process(Counter)
begin
if(Counter=1) then
I1<='0';
else
I1<='1';
end if;
end process plan_I1;
plan_I2: process(Counter)
begin
if(Counter=7) then
I2<='0';
else
I2<='1';
end if;
end process plan_I2;
plan_I3: process(Counter)
begin
if(Counter=13) then
I3<='0';
else
I3<='1';
end if;
end process plan_I3;
plan_I4: process(Counter)
begin
if(Counter=19) then
I4<='0';
else
I4<='1';
end if;
end process plan_I4;
plan_I5: process(Counter)
begin
if(Counter=8) then
I5<='0';
else
I5<='1';
end if;
end process plan_I5;
plan_I6: process(Counter)
begin
if(Counter=10) then
I6<='0';
else
I6<='1';
end if;
end process plan_I6;
plan_I7: process(Counter)
begin
if(Counter=20) then
I7<='0';
else
I7<='1';
end if;
end process plan_I7;
plan_I8: process(Counter)
begin
if(Counter=22) then
I8<='0';
else
I8<='1';
end if;
end process plan_I8;
plan_wrdata: process(I1,I2,I3,I4,I5,I6,I7,I8,djust,unout,unin)------------------------------------------check by soshow on March 6th.
begin
if(unin'event and unin='1' and unout='0' and I1='0' and djust='0') then
channel1L_realdata<=not data;
--databus<=channel1L_realdata;
--InitoutA0<='1';
end if;
if(unin'event and unin='1' and unout='0' and I2='0' and djust='0') then
channel1H_realdata<=not data;
--databus<="0000"&channel1H_realdata(3 downto 0);
end if;
if(unin'event and unin='1' and unout='0' and I5='0' and djust='0') then
databus<=channel1H_realdata;
end if;
if(unin'event and unin='1' and unout='0' and I6='0' and djust='0') then
databus<=channel1L_realdata;
end if;
if(unin'event and unin='1' and unout='0' and I3='0' and djust='0') then
channel2L_realdata<=not data;
--databus<=channel2L_realdata;
--InitoutA1<='1';
end if;
if(unin'event and unin='1' and unout='0' and I4='0' and djust='0') then
channel2H_realdata<=not data;
--databus<="0000"&channel2H_realdata(3 downto 0);
end if;
if(unin'event and unin='1' and unout='0' and I7='0' and djust='0') then
databus<=channel2H_realdata;
end if;
if(unin'event and unin='1' and unout='0' and I8='0' and djust='0') then
databus<=channel2L_realdata;
end if;
---------------------------------------change by soshow 08.3.5
end process plan_wrdata;
--------------------------------------------------------------------
Init_max530: process(Counter)
begin
if(Counter=9) then
P530_0_CS<='0';
P530_WR<='0';
P530_A0A1<='1';
elsif(Counter=11) then
P530_0_CS<='0';
P530_WR<='0';
P530_A0A1<='0';
elsif(Counter=21) then
P530_1_CS<='0';
P530_WR<='0';
P530_A0A1<='1';
elsif(Counter=23) then
P530_1_CS<='0';
P530_WR<='0';
P530_A0A1<='0';
else
P530_0_CS<='1';
P530_1_CS<='1';
P530_WR<='1';
P530_A0A1<='0';
end if;
end process Init_max530;
----------------------------------------------------------------------
--------------------------------------------------------------------
DA_Convert: process(Counter,Counter_LDAC0,Counter_LDAC1)
begin
if(Counter=12) then
Counter_LDAC0<=Counter_LDAC0+1;
if(Counter_LDAC0=24) then
P530_0_LDAC <='0';
elsif(Counter_LDAC0=25) then
Counter_LDAC0<=0;
end if;
--InitoutA0<='1';
else
P530_0_LDAC <='1';
end if;
if(Counter=0) then
Counter_LDAC1<=Counter_LDAC1+1;
if(Counter_LDAC1=24) then
P530_1_LDAC <='0';
elsif(Counter_LDAC1=25) then
Counter_LDAC1<=0;
end if;
--InitoutA1<='1';
else
P530_1_LDAC <='1';
end if;
end process DA_Convert;
-------------------------------------------------------------------
-------------------------------------------------------------------
plan_st: process(wprocess,unout,unin,addr,enable,djust,read_Counter)
begin
if wprocess='0' and unout='1' and djust='0' and enable='0' and unin='0' and addr(3 downto 1)="000" then
curr_st<=s0;
elsif wprocess='0' and unout='1' and djust='0' and enable='0' and unin='0' and addr(3 downto 0)/="0000" then
curr_st<=s1;
elsif wprocess='0' and unout='1' and enable='1' and djust='0' and unin='0' then
curr_st<=s1;
elsif wprocess='1' and unout='1' and enable='1' and unin='0' then
curr_st<=s1;
elsif wprocess='1' and unout='0' and enable='1' then
curr_st<=s2;
elsif wprocess='1' and unout='1' and enable='0' and djust='1' and addr(3 downto 0)="0000" and unin='0' and read_Counter=63 then --------------
--r_flag(7 downto 0)<="11111111";
curr_st<=s3; ----------------------add in2008.1.21
elsif wprocess='1' and unout='1' and enable='0' and djust='1' and addr(3 downto 0)="0001" and unin='0' then
curr_st<=s4;
elsif wprocess='1' and unout='1' and enable='0' and djust='1' and addr(3 downto 0)="0000" and unin='0' and read_Counter<63 then --------------add in 2008.1.21
--r_flag(7 downto 0)<="11111111";
curr_st<=s5;
-- r_flag(7)<=not r_flag(7);
elsif wprocess='1' and unout='1' and enable='0' and djust='0' and addr(3 downto 0)="0001" and unin='0' then curr_st<=s6;
elsif wprocess='1' and unout='1' and unin='0' and enable='0' and addr(3 downto 0)/="0000" and addr(3 downto 0)/="0001" then ---------read.
curr_st<=s7;
elsif wprocess='1' and unout='0' and enable='0' and addr(3 downto 0)/="0000" and addr(3 downto 0)/="0001" then ---------write.
curr_st<=s8;
--elsif(wprocess='1' and unout='0' and addr(3 downto 0)="0001" and enable='0' and djust='0') then ------------ -- curr_st<=s8;
end if;
end process plan_st;
plan_stt: process(wprocess,unout,unin,addr,enable,djust,read_Counterbegin
if( unin'event and unin='1' and unout='0' and addr(3 downto 0)="0001" and enable='0' and djust='1')then
qmem<=data;
elsif(unin'event and unin='1' and wprocess='1' and unout='0' and addr(3 downto 0)="0001" and enable='0' and djust='0') then
qmemm<=data; elsif(unin'event and unin='1' and wprocess='1' and unout='1' and enable='0' and djust='1' and addr(3 downto 0)="0000" and read_Counter=63) then
r_flag(7 downto 0)<="11111111";
r_flag(7)<=not r_flag(7);
end if;
end process plan_stt; ----------------------add in2008.1.21
end www;
-------------------------------------------------------- /// |
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发表于 2008-3-20 17:22:54
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