IPC-7351-Generic_Requirements_for_Surface_Mount_Design_and_Land_Pattern_Stand

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【文件名】:071223@52RD_IPC-7351-Generic_Requirements_for_Surface_Mount_Design_and_Land_Pattern_Standard.pdf
【格　式】:pdf
【大　小】:1018K
【简　介】: This document provides information on land pattern geometries
used for the surface attachment of electronic components.
The intent of the information presented herein is to
provide the appropriate size, shape and tolerance of surface
mount land patterns to insure sufficient area for the appropriate
solder fillet to meet the requirements of IPC/EIA
J-STD-001, and also to allow for inspection, testing, and
rework of those solder joints.

【目　录】: Table of Contents
1 SCOPE ...................................................................... 1
1.1 Purpose ................................................................. 1
1.2 Documentation Hierarchy .................................... 1
1.2.1 Component and Land Pattern Family
Structure ............................................................... 2
1.3 Performance Classification .................................. 2
1.3.1 Producibility Levels ............................................. 2
1.4 Land Pattern Determination ................................ 2
1.5 Terms and Definitions ......................................... 3
2 APPLICABLE DOCUMENTS ................................... 5
2.1 IPC ....................................................................... 5
2.2 Electronic Industries Association ........................ 5
2.3 Joint Industry Standards (IPC) ............................ 5
2.4 International Electrotechnical Commission ........ 6
2.5 Joint Electron Device Engineering Council
(JEDEC) ............................................................... 6
3 DESIGN REQUIREMENTS ....................................... 6
3.1 Dimensioning Systems ........................................ 6
3.1.1 Component Tolerancing ....................................... 6
3.1.2 Land Tolerancing ................................................. 9
3.1.3 Fabrication Allowances ....................................... 9
3.1.4 Assembly Tolerancing ....................................... 10
3.1.5 Dimension and Tolerance Analysis ................... 10
3.2 Design Producibility .......................................... 18
3.2.1 SMT Land Pattern ............................................. 18
3.2.2 Standard Component Selection ......................... 18
3.2.3 Circuit Substrate Development ......................... 18
3.2.4 Assembly Considerations .................................. 18
3.2.5 Provision for Automated Test ............................ 18
3.2.6 Documentation for SMT ................................... 18
3.3 Environmental Constraints ................................ 18
3.3.1 Moisture Sensitive Components ........................ 18
3.3.2 End-Use Environment Considerations .............. 18
3.4 Design Rules ...................................................... 20
3.4.1 Component Spacing ........................................... 20
3.4.2 Single- and Double-Sided Board Assembly ..... 20
3.4.3 Component Stand-off Height for Cleaning ....... 22
3.4.4 Fiducial Marks ................................................... 22
3.4.5 Conductors ......................................................... 24
3.4.6 Via Guidelines ................................................... 24
3.4.7 Standard PCB Fabrication Allowances ............. 27
3.4.8 Panelization ........................................................ 27
3.5 Outer Layer Surface Finishes ............................ 30
3.5.1 Solder Mask Finishes ........................................ 30
3.5.2 Solder Mask Clearances .................................... 30
3.5.3 Land Pattern Surface Finishes ........................... 31
4 COMPONENT QUALITY VALIDATION ................. 31
4.1 Validation Techniques ........................................ 31
5 TESTABILITY .......................................................... 32
5.1 Board and Assembly Test .................................. 32
5.1.1 Bare-Board Test ................................................. 32
5.1.2 Assembled Board Test ....................................... 32
5.2 Nodal Access ..................................................... 33
5.2.1 Test Philosophy .................................................. 33
5.2.2 Test Strategy for Bare Boards ........................... 33
5.3 Full Nodal Access for Assembled Board .......... 33
5.3.1 In-Circuit Test Accommodation ........................ 33
5.3.2 Multi-Probe Testing ........................................... 34
5.4 Limited Nodal Access ....................................... 34
5.5 No Nodal Access ............................................... 34
5.6 Clam-Shell Fixtures Impact ............................... 34
5.7 Printed Board Test Characteristics .................... 35
5.7.1 Test Land Pattern Spacing ................................. 35
5.7.2 Test Land Size and Shape ................................. 35
5.7.3 Design for Test Parameters ............................... 35
6 PRINTED BOARD STRUCTURE TYPES .............. 36
6.1 General Considerations ...................................... 38
6.1.1 Categories ........................................................... 39
6.1.2 Thermal Expansion Mismatch ........................... 39
6.2 Organic-Base Material ....................................... 39
6.3 Nonorganic Base Materials ............................... 39
6.4 Alternative PCB Structures ............................... 39
6.4.1 Supporting-Plane PCB Structures ..................... 39
6.4.2 High-Density PCB Technology ......................... 39
6.4.3 Constraining Core Structures ............................ 39
6.4.4 Porcelainized Metal (Metal Core) Structures ... 39
7 ASSEMBLY CONSIDERATION FOR SURFACE
MOUNT TECHNOLOGY (SMT) .............................. 39
7.1 SMT Assembly Process Sequence .................... 39
7.2 Substrate Preparation ......................................... 40
7.2.1 Adhesive Application ......................................... 40
7.2.2 Conductive Adhesive ......................................... 40
7.2.3 Solder Paste Application ................................... 40
7.2.4 Solder Preforms ................................................. 41
7.3 Component Placement ....................................... 41
IPC-7351 February 2005
iv
7.3.1 Component Data Transfer ................................. 41
7.4 Soldering Processes ........................................... 42
7.4.1 Wave Soldering .................................................. 42
7.4.2 Vapor Phase (VP) Soldering ............................. 42
7.4.3 IR Reflow Soldering .......................................... 43
7.4.4 Hot Air/Gas Convection Soldering ................... 43
7.4.5 Laser Reflow Soldering ..................................... 43
7.4.6 Conduction Reflow Soldering ........................... 43
7.5 Cleaning ............................................................. 43
7.6 Repair/Rework ................................................... 43
7.6.1 Heatsink Effects ................................................. 43
7.6.2 Dependence on Printed Board
Material Type ..................................................... 44
7.6.3 Dependence on Copper Land and
Conductor Layout .............................................. 44
8 IPC-7352 DISCRETE COMPONENTS ................... 44
8.1 Chip Resistors (RESC) ...................................... 44
8.1.1 Basic Construction ............................................. 45
8.1.2 Marking .............................................................. 45
8.1.3 Carrier Package Format ..................................... 45
8.1.4 Resistance to Soldering ..................................... 45
8.2 Chip Capacitors (CAPC) ................................... 45
8.2.1 Basic Construction ............................................. 45
8.2.2 Marking .............................................................. 45
8.2.3 Carrier Package Format ..................................... 45
8.2.4 Resistance to Soldering ..................................... 45
8.3 Inductors (INDC, INDM, INDP) ...................... 45
8.3.1 Basic Construction ............................................. 45
8.3.2 Marking .............................................................. 45
8.3.3 Carrier Package Format ..................................... 45
8.3.4 Resistance to Soldering ..................................... 45
8.4 Tantalum Capacitors (CAPT) ............................ 45
8.4.1 Basic Construction ............................................. 46
8.4.2 Marking .............................................................. 46
8.4.3 Carrier Package Format ..................................... 46
8.4.4 Resistance to Soldering ..................................... 46
8.5 Metal Electrode Face Diodes (DIOMELF,
RESMELF) ........................................................ 47
8.5.1 Basic Construction ............................................. 47
8.5.2 Marking .............................................................. 47
8.5.3 Carrier Package Format ..................................... 47
8.5.4 Resistance to Soldering ..................................... 47
8.6 SOT23 ................................................................ 47
8.6.1 Basic Construction ............................................. 47
8.6.2 Marking .............................................................. 47
8.6.3 Carrier Package Format ..................................... 47
8.6.4 Resistance to Soldering ..................................... 47
8.7 SOT89 ................................................................ 47
8.7.1 Basic Construction ............................................. 47
8.7.2 Marking .............................................................. 48
8.7.3 Carrier Package Format ..................................... 48
8.7.4 Resistance to Soldering ..................................... 48
8.8 SOD123 .............................................................. 48
8.8.1 Basic Construction ............................................. 48
8.8.2 Marking .............................................................. 48
8.8.3 Carrier Package Format ..................................... 48
8.8.4 Resistance to Soldering ..................................... 48
8.9 SOT143 .............................................................. 48
8.9.1 Basic Construction ............................................. 48
8.9.2 Marking .............................................................. 48
8.9.3 Carrier Package Format ..................................... 48
8.9.4 Resistance to Soldering ..................................... 48
8.10 SOT223 .............................................................. 48
8.10.1 Basic Construction ............................................. 49
8.10.2 Marking .............................................................. 49
8.10.3 Carrier Package Format ..................................... 49
8.10.4 Resistance to Soldering ..................................... 49
8.11 TO252 (DPAK Type) ......................................... 49
8.11.1 Basic Construction ............................................. 49
8.11.2 Marking .............................................................. 49
8.11.3 Carrier Package Format ..................................... 49
8.11.4 Resistance to Soldering ..................................... 49
8.12 Molded Body Diode (DIOSMB) ....................... 49
9 IPC-7353 GULLWING LEADED COMPONENTS,
TWO SIDES ............................................................ 49
9.1 SOIC ................................................................... 50
9.1.1 Basic Construction ............................................. 50
9.1.2 Marking .............................................................. 50
9.1.3 Carrier Package Format ..................................... 50
9.1.4 Resistance to Soldering ..................................... 50
9.2 SOP8/SOP63 (SSOIC) ....................................... 50
9.2.1 Basic Construction ............................................. 50
9.2.2 Marking .............................................................. 50
9.2.3 Carrier Package Format ..................................... 50
9.2.4 Resistance to Soldering ..................................... 50
9.3 SOP127 (SOP-IPC-782) .................................... 50
9.3.1 Marking .............................................................. 51
9.3.2 Carrier Package Format ..................................... 51
9.3.3 Resistance to Soldering ..................................... 51
9.4 TSSOPS ............................................................. 51
9.4.1 Marking .............................................................. 51
9.4.2 Carrier Packages Format ................................... 51
February 2005 IPC-7351
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9.4.3 Resistance to Soldering ..................................... 51
9.5 CFP127 ............................................................... 51
9.5.1 Marking .............................................................. 51
9.5.2 Carrier Packages Format ................................... 51
9.5.3 Resistance to Soldering ..................................... 52
10 IPC-7354 J-LEADED COMPONENTS,
TWO SIDES .......................................................... 52
10.1 Basic Construction ............................................. 52
10.2 Marking .............................................................. 52
10.3 Carrier Package Format ..................................... 52
10.4 Process Considerations ...................................... 52
11 IPC-7355 GULL-WING LEADED
COMPONENTS, FOUR SIDES ............................. 52
11.1 BQFP (PQFP) .................................................... 53
11.1.1 Carrier Package Format ..................................... 53
11.2 SQFP/QFP .......................................................... 53
11.2.1 Carrier Package Format ..................................... 53
11.3 QFPR .................................................................. 54
11.3.1 Carrier Package Format ..................................... 54
11.4 CQFP .................................................................. 54
11.4.1 Carrier Package Format ..................................... 54
12 IPC-7356 J LEADED COMPONENTS,
FOUR SIDES ......................................................... 54
12.1 PLCC .................................................................. 55
12.1.1 Premolded Plastic Chip Carriers ....................... 55
12.1.2 Postmolded Plastic Chip Carriers ..................... 55
12.2 PLCCR ............................................................... 55
12.2.1 Premolded Plastic Chip Carriers ....................... 56
12.2.2 Postmolded Plastic Chip Carriers ..................... 56
13 IPC-7357 POST (DIP) LEADS, TWO SIDES ...... 56
13.1 Termination Materials ........................................ 56
13.2 Marking .............................................................. 56
13.3 Carrier Package Format ..................................... 56
13.4 Resistance to Soldering ..................................... 56
14 IPC-7358 AREA ARRAY COMPONENTS
(BGA, FBGA, CGA) .............................................. 57
14.1 Area Array Configurations ................................ 57
14.1.1 BGA Packages ................................................... 57
14.1.2 Fine Pitch BGA Package (FBGA) .................... 58
14.1.3 Ceramic Column Grid Arrays (CGA) ............... 58
14.2 General Configuration Issues ............................ 59
14.2.1 Device Outlines ................................................. 59
14.2.2 Contact Matrix Options ..................................... 59
14.2.3 Selective Depopulation ...................................... 60
14.2.4 Attachment Site Planning .................................. 60
14.2.5 Defining Contact Assignment ............................ 61
14.3 Handling and Shipping ...................................... 61
14.4 Land Pattern Analysis ........................................ 61
14.4.1 Land Approximation .......................................... 61
14.4.2 Total Variation .................................................... 61
14.4.3 Future Ball Conditions ...................................... 62
14.4.4 Land Pattern Calculator ..................................... 62
15 IPC-7359 NO LEAD COMPONENTS (QFN,
SON, LCC) ............................................................ 62
15.1 LCC .................................................................... 62
15.1.1 Marking .............................................................. 63
15.1.2 Carrier Package Format ..................................... 63
15.1.3 Process Considerations ...................................... 63
15.2 Quad Flat No-Lead (QFN) ................................ 63
15.2.1 Marking .............................................................. 64
15.2.2 Carrier Package Format ..................................... 64
15.2.3 Process Considerations ...................................... 64
15.2.4 Solder Resist Considerations ............................. 64
15.3 Small Outline No-Lead (SON) ......................... 64
15.3.1 Marking .............................................................. 64
15.3.2 Carrier Package Format ..................................... 65
15.3.3 Process Considerations ...................................... 65
15.3.4 Solder Resist Considerations ............................. 65
16 ZERO COMPONENT ORIENTATIONS ................ 65
APPENDIX A (Informative) Test Patterns –
Process Evaluations ......................... 71
APPENDIX B (Informative) Abbreviations
and Definitions .................................. 73
APPENDIX C IPC-7351 Land Pattern Viewer ......... 74

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