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【文件名】:06112@52RD_High Performance Pipeline AD Converter .pdf
【格 式】:pdf
【大 小】:1178K
【简 介】:
1
Analog-to-digital converters (ADCs) are key design blocks in modern
microelectronic digital communication systems. With the fast advancement of
CMOS fabrication technology, more and more signal-processing functions are
implemented in the digital domain for a lower cost, lower power consumption,
higher yield, and higher re-configurability. This has recently generated a great
demand for low-power, low-voltage ADCs that can be realized in a mainstream
deep-submicron CMOS technology.
Intended for embedded communication applications, specifications of these
converters emphasize high dynamic range and low spurious spectral performance.
For example, the worst-case blocking specs of some wireless standards, such as
GSM, dictate a conversion linearity of 14-16 bits to avoid losing a weak received
signal due to distortion artifacts. It is nontrivial to achieve this level of linearity in
2
a monolithic environment where post-fabrication component trimming or
calibration is cumbersome to implement for certain applications or/and for cost
and manufacturability reasons.
Another hurdle to achieve full system integration stems from the power
efficiency of the A/D interface circuits supplied by a low voltage dictated by the
gate-oxide reliability of the deeply scaled digital CMOS devices. It has been
observed recently that these interface analog/mixed-signal circuits are gobbling a
larger chunk of the chip area as well as total power consumption; hence it
becomes essential to accomplish an optimized design from both the architecture
and the circuit standpoints. To achieve high linearity, high dynamic range, and
high sampling speed simultaneously under low supply voltages in deepsubmicron
CMOS technology with low power consumption has thus far been
conceived of as extremely challenging.
This thesis addresses these challenges using the pipeline ADC as a
demonstration platform. Specific new design techniques/algorithms include (1) a
power-efficient, capacitor ratio-independent conversion scheme, (2) a pipeline
stage-scaling algorithm, (3) a nested CMOS gain-boosting technique, (4) a ∆Σ
common-mode voltage regulation circuit, (5) an amplifier and comparator sharing
technique, and the use of minimum channel-length, thin oxide transistors with
clock bootstrapping and in-line switch techniques. The prototype design of a 14-
3
bit pipeline ADC fabricated in a 0.18- µm CMOS technology that achieves an over
100-dB spurious-free dynamic range (SFDR) demonstrates the effectiveness of
these techniques.
【目 录】:
iv
List of Figures................................................................................................. vi
List of Tables.................................................................................................. ix
Chapter 1 Introduction................................................................................ 1
1.1 Wireless Communication ............................................................. 1
1.2 Challenges of Broadband Radio................................................... 3
1.3 CMOS Technology Scaling ......................................................... 5
1.4 A/D Interface ................................................................................ 8
1.5 Research Contribution ................................................................ 10
1.6 Thesis Organization.................................................................... 11
Chapter 2 Pipeline Architecture Power Efficiency................................ 14
2.1 Pipeline ADC Architecture ........................................................ 14
2.2 Power Efficiency under Low Supply Voltage ........................... 17
2.2.1 C kT / Noise...................................................................... 17
2.2.2 Power Consumption of Pipeline ADC.............................. 18
2.3 Stage-Scaling Analysis of Pipeline ADC .................................. 20
2.3.1 Cline-Gray Model ............................................................. 21
2.3.2 Parasitic-Loaded Amplifier Model ................................... 22
2.3.3 Stage-Scaling Analysis Revisited ..................................... 25
2.3.4 Summary............................................................................ 28
2.3.4.1 Speed Factor............................................................. 29
2.3.4.2 Taper Factor ............................................................. 30
Chapter 3 Capacitor Error-Averaging.................................................... 35
3.1 Pipeline ADC Error Mechanism................................................ 36
3.2 Capacitor Matching Accuracy.................................................... 38
v
3.3 Precision Conversion Techniques.............................................. 40
3.3.1 Active Capacitor Error-Averaging.................................... 42
3.3.2 Passive Capacitor Error-Averaging – Part I ..................... 44
3.3.3 Passive Capacitor Error-Averaging – Part II.................... 47
3.3.4 Power Efficiency ............................................................... 48
3.3.5 Monte Carlo Simulation.................................................... 49
Appendix
A3.1 MDAC Capacitor Matching.................................................... 52
A3.2 Active CEA.............................................................................. 54
A3.3 Passive CEA (I) ....................................................................... 56
A3.4 Passive CEA (II) ...................................................................... 58
Chapter 4 Prototype Design...................................................................... 62
4.1 Sampling Clock Skew ................................................................ 62
4.2 Amplifier and Sub-ADC Sharing............................................... 64
4.3 Nested CMOS Gain Boosting .................................................... 68
4.4 Discrete-Time Common-Mode Regulation ............................... 69
4.5 Dynamic Comparator ................................................................. 73
4.6 Sampling Switch......................................................................... 74
Appendix
A4.1 Discrete-Time Common-Mode Regulation ............................ 75
Chapter 5 Experimental Results .............................................................. 79
5.1 Static Linearity............................................................................ 80
5.2 Dynamic Linearity...................................................................... 82
5.2.1 SNDR, THD, and SFDR................................................... 82
5.2.2 ADC Performance Sensitivity........................................... 84
Chapter 6 Conclusion ................................................................................ 87
vi
List of Figures
Figure 1.1 Ericsson single-chip 0.18- µm CMOS Bluetooth radio
(2001). .....................................................................................1
Figure 1.2 Scaling trend of silicon CMOS according to the 2003
edition international technology roadmap of
semiconductor (ITRS).3 ...........................................................6
Figure 1.3 (a) Simplified block diagram of a direct-conversion RF
receiver. Shaded blocks are off-chip components. (b)
Simplified block diagram of a double-conversion
receiver. (c) Signal spectrum at point A (after antenna)
and B (before ADC). ...............................................................9
Figure 2.1 Block diagram of a pipeline A/D converter...........................15
Figure 2.2 Circuit diagram of the 1.5-b/s MDAC. ..................................16
Figure 2.3 Noise model of MDAC including parasitic loading
effects. ...................................................................................22
Figure 2.4 Evaluation of ) , , ( η γ n g versus the scaling factor γ...............29
Figure 2.5 Evaluation of ) , , ( η γ n g versus the speed factor η. ...............30
Figure 2.6 Evaluation of ) , , ( η γ n g versus the taper factor x. .................31
Figure 2.7 Evaluation of opt γ versus the stage resolution n....................32
Figure 3.1 Voltage transfer characteristic of a 1.5-b/s residue gain
stage. The solid curve shows the ideal transfer function
and the dashed one exhibits static nonlinearity due to
analog circuit non-idealities. .................................................37
Figure 3.2 Circuit diagram of an n-b/s pipeline ADC and its
residue transfer characteristic. (a) Sampling mode. (b)
vii
Amplification mode...............................................................38
Figure 3.3 Capacitor matching accuracy versus stage resolution
for a 14-bit pipeline ADC. A half LSB maximum DNL
and INL error is assumed. .....................................................40
Figure 3.4 Circuit diagram of the active CEA technique. The stage
operates on a three-phase clock. φ1 is the sampling
phase (not shown). φ2 and φ3 are the amplification
phases shown in (a) and (b), respectively..............................43
Figure 3.5 Voltage waveforms of the active CEA gain stage of
Figure 3.4...............................................................................44
Figure 3.6 Circuit diagram of the passive CEA technique (I). C1
and C2 are the sampling capacitors of the current
pipeline stage, while C3 and C4 are from the trailing
stage.......................................................................................45
Figure 3.7 Voltage waveforms of the passive CEA gain stages of
Figure 3.6 and Figure 3.8. .....................................................46
Figure 3.8 Circuit diagram of the passive CEA technique (II).
Here C3 and C4 are also the sampling capacitors from
the trailing stage. ...................................................................47
Figure 3.9 Results of the Monte Carlo yield simulation. 14-bit
INL and DNL are achieved with a 6-bit capacitor
matching accuracy (3 σ). Amplifier gain is assumed to
be large (100 dB). ..................................................................51
Figure 4.1 Sampling clock skew in the front-end pipeline stage. ...........62
Figure 4.2 Block diagram of the 14-b pipeline ADC. .............................64
Figure 4.3 Potential summing node crosstalk through the parasitic
capacitance of off switches....................................................65
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Figure 4.4 (a) Timing diagram. (b) Summing node crosstalk path
during the falling edge of φ1. ................................................65
Figure 4.5 (a) Modified timing diagram. (b) Dummy switches. .............66
Figure 4.6 Nested CMOS gain-boosted amplifier...................................68
Figure 4.7 (a) ∆Σ common-mode regulation circuit. (b) Timing
diagram. .................................................................................70
Figure 4.8 (a) Discrete-time integrator with look-ahead capacitor
CA. (b) Averaging and differencing amplifier. (c)
Common-mode feedback and feedforward connections
of the six pipeline stages........................................................71
Figure 4.9 Pole-zero and frequency response plots of the CMFB
loop. .......................................................................................73
Figure 4.10 (a) Dynamic comparator. (b) Timing diagram. ...................74
Figure 4.11 (a) Integrator in φA (sampling). (b) Integrator in φB
(integration). (c) Timing diagram. .......................................75
Figure 5.1 Die photo of the prototype 14-b pipeline ADC. ....................79
Figure 5.2 Measured DNL and INL (fs = 12 MS/s, fin = 1 MHz)............80
Figure 5.3 Measured ADC performance versus input signal level.
(a) fs = 12 MS/s, fin = 1.01 MHz. (b) fs = 12 MS/s, fin
= 5.47 MHz............................................................................81
Figure 5.4 FFT spectrum at fin = (a) 1 MHz, (b) 5 MHz, and (c) 40
MHz.......................................................................................83
Figure 5.5 Measured dynamic performance............................................84
Figure 5.6 Measured performance versus Vdd. ........................................84
Figure 5.7 Measured performance versus Vcm.........................................85
Figure 6.1 Comparison of this design (square) and previously
published high-resolution ADCs (diamonds)........................88
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