CIRCUIT TECHNIQUES FOR LOW-VOLTAGE AND HIGH-SPEED ADC

Amay

<P>
<B>【文件名】:06110@52RD_CIRCUIT TECHNIQUES FOR LOW-VOLTAGE AND HIGH-SPEED ADC.part1.rar</B>
<B>【格　式】:rar</B>
<B>【大　小】:3300K</B>
<B>【简　介】:</B></P>
<P>Helsinki University of Technology, Electronic Circuit Design Laboratory
Report 33, Espoo 2002</P>
<P>
<b><FONT size=3>CIRCUIT TECHNIQUES FOR LOW-VOLTAGE
AND HIGH-SPEED A/D CONVERTERS</FONT></b></P><b><FONT size=3></FONT></b>
<P>
<b>Mikko Waltari</b></P>
<P>
Dissertation for the degree of Doctor of Science in Technology to be presented with due permission
of the Department of Electrical and Communications Engineering for public examination
and debate in Auditorium S4 at Helsinki University of Technology (Espoo, Finland) on the 24th
of June, 2002, at 12 o’clock noon.</P>
<P>
Helsinki University of Technology
Department of Electrical and Communications Engineering
Electronic Circuit Design Laboratory
Teknillinen korkeakoulu
S&auml;hk&ouml;- ja tietoliikennetekniikan osasto
Piiritekniikan laboratorio</P>

<P><b><FONT size=4>Abstract</FONT></b></P>
<P><b></b>
The increasing digitalization in all spheres of electronics applications, from telecommunications
systems to consumer electronics appliances, requires analog-to-digital
converters (ADCs) with a higher sampling rate, higher resolution, and lower power
consumption. The evolution of integrated circuit technologies partially helps in meeting
these requirements by providing faster devices and allowing for the realization
of more complex functions in a given silicon area, but simultaneously it brings new
challenges, the most important of which is the decreasing supply voltage.
Based on the switched capacitor (SC) technique, the pipelined architecture has
most successfully exploited the features of CMOS technology in realizing high-speed
high-resolution ADCs. An analysis of the effects of the supply voltage and technology
scaling on SC circuits is carried out, and it shows that benefits can be expected at
least for the next few technology generations. The operational amplifier is a central
building block in SC circuits, and thus a comparison of the topologies and their low
voltage capabilities is presented.
It is well-known that the SC technique in its standard form is not suitable for
very low supply voltages, mainly because of insufficient switch control voltage. Two
low-voltage modifications are investigated: switch bootstrapping and the switched
opamp (SO) technique. Improved circuit structures are proposed for both. Two ADC
prototypes using the SO technique are presented, while bootstrapped switches are
utilized in three other prototypes.
An integral part of an ADC is the front-end sample-and-hold (S/H) circuit. At high
signal frequencies its linearity is predominantly determined by the switches utilized.
A review of S/H architectures is presented, and switch linearization by means of bootstrapping
is studied and applied to two of the prototypes. Another important parameter
is sampling clock jitter, which is analyzed and then minimized with carefully-designed
clock generation and buffering.
The throughput of ADCs can be increased by using parallelism. This is demon-
ii
strated on the circuit level with the double-sampling technique, which is applied to
S/H circuits and a pipelined ADC. An analysis of nonidealities in double-sampling
is presented. At the system level parallelism is utilized in a time-interleaved ADC.
The mismatch of parallel signal paths produces errors, for the elimination of which a
timing skew insensitive sampling circuit and a digital offset calibration are developed.
A total of seven prototypes are presented: two double-sampled S/H circuits, a
time-interleaved ADC, an IF-sampling self-calibrated pipelined ADC, a current steering
DAC with a deglitcher, and two pipelined ADCs employing the SO technique.
Keywords: analog integrated circuit, analog-to-digital conversion, BiCMOS, bootstrapped
switch, CMOS, double-sampling, IF-sampling, low voltage, operational amplifier,
pipelined analog-to-digital converter, sample-and-hold circuit, switched-capacitor,
switched-opamp, time interleaving.
<B>【目　录】:</B>

Amay

<P><b><FONT size=5>Contents</FONT></b></P><b><FONT size=5></FONT></b>
<P>
<b>Abstract i</b>
<b>Preface iii</b>
<b>Contents v</b>
<b>Symbols and Abbreviations xii</b>
1 Introduction 1
1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Organization of the Thesis and Research Contributions . . . . . . . . 2
2 Low Voltage Issues 5
2.1 Signal-to-Noise Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Circuit Speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3.1 Saturated MOSFET in Strong Inversion . . . . . . . . . . . . 9
2.3.2 Saturated MOSFET in Weak Inversion . . . . . . . . . . . . . 10
2.3.3 Slew Rate Limited Power Consumption . . . . . . . . . . . . 10
2.3.4 Technology Impact . . . . . . . . . . . . . . . . . . . . . . . 11
2.3.5 Power Consumption: Summary and Conclusions . . . . . . . 11
2.4 Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.5 Operational Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.6 MOS Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.7 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3 Sample-and-Hold Operation 21
3.1 S/H Basics and Performance Metrics . . . . . . . . . . . . . . . . . . 21
3.2 Spectra of Sampled Signals . . . . . . . . . . . . . . . . . . . . . . . 23
vi
3.2.1 Spectrum of a Sampled and Held Signal . . . . . . . . . . . . 24
3.2.2 Sampling Function . . . . . . . . . . . . . . . . . . . . . . . 26
3.3 Noise Issues in S/H Circuits . . . . . . . . . . . . . . . . . . . . . . 27
3.3.1 kT/C Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.3.2 Jitter in Sampling Clock . . . . . . . . . . . . . . . . . . . . 28
3.3.3 Other Noise Sources . . . . . . . . . . . . . . . . . . . . . . 29
3.4 Basic S/H Circuit Architectures . . . . . . . . . . . . . . . . . . . . . 29
3.4.1 Open-Loop Architectures . . . . . . . . . . . . . . . . . . . . 30
3.4.2 Closed-Loop Architectures . . . . . . . . . . . . . . . . . . . 30
4 A/D Converters 32
4.1 A/D Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.1.1 Direct Quantization . . . . . . . . . . . . . . . . . . . . . . . 33
4.1.2 Quantization After Analog Preprocessing . . . . . . . . . . . 34
4.1.3 ADC Figures of Merit . . . . . . . . . . . . . . . . . . . . . 34
4.2 Flash ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.3 Subranging ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.4 Folding-and-Interpolating ADC . . . . . . . . . . . . . . . . . . . . 39
4.4.1 Folding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4.4.2 Interpolation . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.4.3 ADC Architecture . . . . . . . . . . . . . . . . . . . . . . . 41
4.4.4 Limitations and Improvements . . . . . . . . . . . . . . . . . 42
4.5 Pipelined ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.5.1 Pipelined A/D Conversion: Principle . . . . . . . . . . . . . 43
4.5.1.1 Operation of a Pipeline Stage . . . . . . . . . . . . 44
4.5.1.2 Forming the Output Code . . . . . . . . . . . . . . 44
4.5.2 Pipeline Architecture . . . . . . . . . . . . . . . . . . . . . . 45
4.5.3 RSD Correction . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.5.4 Switched Capacitor Realization . . . . . . . . . . . . . . . . 47
4.5.5 Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.5.6 Per-Stage Resolution . . . . . . . . . . . . . . . . . . . . . . 50
4.5.6.1 Opamp DC Gain . . . . . . . . . . . . . . . . . . . 50
4.5.6.2 Capacitor Matching . . . . . . . . . . . . . . . . . 51
4.5.6.3 Opamp Bandwidth . . . . . . . . . . . . . . . . . . 51
4.5.7 Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
4.6 Time-Interleaved ADC . . . . . . . . . . . . . . . . . . . . . . . . . 56
4.6.1 Problems and Solutions . . . . . . . . . . . . . . . . . . . . 57
vii
4.7 A/D Converters: Summary . . . . . . . . . . . . . . . . . . . . . . . 58
5 S/H Circuit Architectures 59
5.1 Bipolar Architectures . . . . . . . . . . . . . . . . . . . . . . . . . . 59
5.1.1 Diode Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . 59
5.1.2 Switched Emitter Follower . . . . . . . . . . . . . . . . . . . 60
5.2 CMOS Architectures . . . . . . . . . . . . . . . . . . . . . . . . . . 61
5.2.1 S/H Circuit with Source Follower Buffer . . . . . . . . . . . 62
5.2.2 S/H Circuit Using Miller Capacitance . . . . . . . . . . . . . 65
5.2.3 Switched Transconductance S/H Architecture . . . . . . . . . 66
5.2.4 Closed-Loop S/H Circuit with Resistor Ratio Defined Gain . . 67
5.2.5 S/H Circuit with Capacitor Ratio Defined Gain . . . . . . . . 68
5.2.6 S/H Circuit without a Reset Phase . . . . . . . . . . . . . . . 69
6 Sampling with a MOS Transistor Switch 71
6.1 Voltage-Dependent Turn-Off Moment . . . . . . . . . . . . . . . . . 72
6.2 Charge Injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
6.3 Bottom Plate Sampling . . . . . . . . . . . . . . . . . . . . . . . . . 78
6.4 Nonlinear Time Constant . . . . . . . . . . . . . . . . . . . . . . . . 79
6.4.1 Linearization of Basic Switches . . . . . . . . . . . . . . . . 81
6.4.2 Gate Voltage Boosting . . . . . . . . . . . . . . . . . . . . . 82
6.4.3 Bootstrapped Switches . . . . . . . . . . . . . . . . . . . . . 83
6.4.3.1 Principle . . . . . . . . . . . . . . . . . . . . . . . 84
6.4.3.2 Circuits from the Literature . . . . . . . . . . . . . 85
6.4.3.3 Eliminating the Bulk Effect . . . . . . . . . . . . . 86
6.4.3.4 Double-Side Bootstrapping . . . . . . . . . . . . . 90
6.4.3.5 Reducing Feedthrough . . . . . . . . . . . . . . . . 91
6.4.3.6 Bootstrapped Switch as a Sampling Switch . . . . . 93
6.5 Sampling Function . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
7 Operational Amplifiers 95
7.1 Requirements for SC Applications . . . . . . . . . . . . . . . . . . . 95
7.1.1 Output Impedance . . . . . . . . . . . . . . . . . . . . . . . 96
7.1.2 Output Voltage Range . . . . . . . . . . . . . . . . . . . . . 96
7.1.3 Input Common Mode Range . . . . . . . . . . . . . . . . . . 96
7.1.4 DC Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
7.1.5 Bandwidth and Phase Margin . . . . . . . . . . . . . . . . . 97
7.1.6 Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
viii
7.1.7 Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
7.2 OTAs with Single High-Gain Stage . . . . . . . . . . . . . . . . . . . 100
7.2.1 Telescopic OTA . . . . . . . . . . . . . . . . . . . . . . . . . 101
7.2.2 Folded Cascode OTA . . . . . . . . . . . . . . . . . . . . . . 101
7.2.3 Cascode Stage with Low-Gain Preamplifier . . . . . . . . . . 103
7.2.4 Comparison of Single-Stage OTAs . . . . . . . . . . . . . . . 104
7.2.5 Gain Enhancement Techniques . . . . . . . . . . . . . . . . . 104
7.3 Two-Stage Opamps . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
7.3.1 Miller Opamp . . . . . . . . . . . . . . . . . . . . . . . . . . 107
7.3.2 High-Gain First Stage and Rail-to-Rail Output Stage . . . . . 107
7.3.2.1 Frequency Compensation . . . . . . . . . . . . . . 109
7.3.2.2 Two-Stage BiCMOS Opamp . . . . . . . . . . . . 110
8 Clock Generation 112
8.1 Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
8.1.1 Jitter Sources . . . . . . . . . . . . . . . . . . . . . . . . . . 113
8.1.2 Inverter Buffer . . . . . . . . . . . . . . . . . . . . . . . . . 115
8.2 Signal Crosstalk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
8.3 Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
8.3.1 Standard Non-overlapping Clock Generator . . . . . . . . . . 117
8.3.2 DLL-Based Clock Generator . . . . . . . . . . . . . . . . . . 118
9 Double-Sampling 121
9.1 Principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
9.2 Nonidealities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
9.2.1 Memory effect . . . . . . . . . . . . . . . . . . . . . . . . . 123
9.2.2 Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
9.2.3 Gain Error . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
9.2.4 Timing Skew . . . . . . . . . . . . . . . . . . . . . . . . . . 126
9.3 Skew-Insensitive Circuit . . . . . . . . . . . . . . . . . . . . . . . . 130
10 Switched Opamp Technique 133
10.1 Operation Principle . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
10.2 Compensating Common Mode Voltage Step . . . . . . . . . . . . . . 135
10.3 Preventing Charge Leakage from Virtual Ground . . . . . . . . . . . 136
10.4 Speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
10.5 Power Supply Rejection and Noise . . . . . . . . . . . . . . . . . . . 139
10.6 Switchable Opamps . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
ix
10.6.1 Circuits from the Literature . . . . . . . . . . . . . . . . . . 141
10.6.1.1 Steyaert’s Switchable Opamp . . . . . . . . . . . . 141
10.6.1.2 Fully Differential Switchable Opamp . . . . . . . . 141
10.6.1.3 Class AB Switchable Opamp . . . . . . . . . . . . 143
10.6.2 Proposed Opamps . . . . . . . . . . . . . . . . . . . . . . . 144
10.6.2.1 Opamp1 . . . . . . . . . . . . . . . . . . . . . . . 144
10.6.2.2 Opamp2 . . . . . . . . . . . . . . . . . . . . . . . 145
10.6.2.3 Opamp3 . . . . . . . . . . . . . . . . . . . . . . . 148
10.6.3 Switchable Opamps: Comparison . . . . . . . . . . . . . . . 152
10.7 Input Interfaces for SO Circuits . . . . . . . . . . . . . . . . . . . . . 152
10.7.1 Active Input Structures . . . . . . . . . . . . . . . . . . . . . 153
10.7.2 Passive Input Interface . . . . . . . . . . . . . . . . . . . . . 155
11 Other Low Voltage Techniques and Building Blocks 159
11.1 Low Voltage SC Technique with Unity-Gain-Reset Opamps . . . . . . 159
11.2 Current Sources and Mirrors . . . . . . . . . . . . . . . . . . . . . . 161
11.3 Bandgap References . . . . . . . . . . . . . . . . . . . . . . . . . . 162
11.3.1 Low Voltage BGR Circuits . . . . . . . . . . . . . . . . . . . 163
11.3.2 Reference Voltage Driver . . . . . . . . . . . . . . . . . . . . 165
12 Prototypes and Experimental Results 166
12.1 Measurement Setups and Methods . . . . . . . . . . . . . . . . . . . 166
12.1.1 Measuring Dynamic Performance of S/H Circuits . . . . . . . 166
12.1.2 ADC Measurements . . . . . . . . . . . . . . . . . . . . . . 167
12.1.2.1 Static Linearity . . . . . . . . . . . . . . . . . . . 168
12.1.2.2 Signal to Noise and Distortion Ratio . . . . . . . . 168
12.2 S/H Circuit Using Double-Sampling . . . . . . . . . . . . . . . . . . 169
12.2.1 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
12.2.2 Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
12.2.3 Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . 171
12.2.4 Opamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
12.2.5 Experimental Results . . . . . . . . . . . . . . . . . . . . . . 172
12.3 Timing Skew-Insensitive Double-Sampling S/H . . . . . . . . . . . . 176
12.3.1 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
12.3.2 Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . 176
12.3.3 Simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
12.3.4 Experimental Results . . . . . . . . . . . . . . . . . . . . . . 178
x
12.4 10-Bit, 200-MS/s Parallel Pipeline ADC . . . . . . . . . . . . . . . . 180
12.4.1 ADC Architecture . . . . . . . . . . . . . . . . . . . . . . . 181
12.4.2 Front-End S/H Circuit . . . . . . . . . . . . . . . . . . . . . 181
12.4.3 Component ADCs . . . . . . . . . . . . . . . . . . . . . . . 183
12.4.4 Reference Voltage Driver . . . . . . . . . . . . . . . . . . . . 186
12.4.5 Digital Offset Calibration . . . . . . . . . . . . . . . . . . . 186
12.4.6 Experimental Results . . . . . . . . . . . . . . . . . . . . . . 188
12.5 13-Bit Self-Calibrated IF-Sampling Pipelined ADC . . . . . . . . . . 191
12.5.1 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
12.5.2 Front-end S/H Circuit . . . . . . . . . . . . . . . . . . . . . 193
12.5.3 Opamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
12.5.4 Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
12.5.5 Clock Buffer and Clock Generator . . . . . . . . . . . . . . . 195
12.5.6 DLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
12.5.7 Self-Calibrated Pipeline A/D Converter . . . . . . . . . . . . 196
12.5.8 Calibration Circuitry . . . . . . . . . . . . . . . . . . . . . . 199
12.5.9 Measurements of the Front-End . . . . . . . . . . . . . . . . 201
12.5.9.1 On-Chip Circuitry . . . . . . . . . . . . . . . . . . 202
12.5.9.2 PCB . . . . . . . . . . . . . . . . . . . . . . . . . 202
12.5.9.3 Equipment . . . . . . . . . . . . . . . . . . . . . . 204
12.5.9.4 Functionality . . . . . . . . . . . . . . . . . . . . . 204
12.5.9.5 Problems and Difficulties . . . . . . . . . . . . . . 205
12.5.9.6 Low Frequency Results . . . . . . . . . . . . . . . 206
12.5.9.7 IF Results . . . . . . . . . . . . . . . . . . . . . . 206
12.5.10 ADC Experimental Results . . . . . . . . . . . . . . . . . . . 209
12.6 Deglitcher for Current Steering DACs . . . . . . . . . . . . . . . . . 213
12.6.1 Introduction to Current Steering DACs . . . . . . . . . . . . 213
12.6.2 Circuit Description . . . . . . . . . . . . . . . . . . . . . . . 214
12.6.2.1 Architecture . . . . . . . . . . . . . . . . . . . . . 214
12.6.2.2 Deglitcher . . . . . . . . . . . . . . . . . . . . . . 215
12.6.2.3 Current Switches . . . . . . . . . . . . . . . . . . 217
12.6.2.4 Current Memory . . . . . . . . . . . . . . . . . . . 218
12.6.2.5 Limitations . . . . . . . . . . . . . . . . . . . . . . 221
12.6.3 Simulations and Experimental Results . . . . . . . . . . . . 223
12.6.4 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
12.7 1st Switched Opamp Pipelined ADC . . . . . . . . . . . . . . . . . . 224
12.7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
xi
12.7.2 ADC Architecture . . . . . . . . . . . . . . . . . . . . . . . 225
12.7.3 MDAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
12.7.4 Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
12.7.5 Input Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
12.7.6 Experimental Results . . . . . . . . . . . . . . . . . . . . . . 227
12.8 2nd Switched Opamp Pipelined ADC . . . . . . . . . . . . . . . . . 231
12.8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
12.8.2 MDAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
12.8.3 Input Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
12.8.4 Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
12.8.5 Experimental Results . . . . . . . . . . . . . . . . . . . . . . 234
Conclusions 239
References 241
A Derivation of OTA GBW Requirement 263
B Optimum Input Capacitance 266
C Saturation Voltage 268</P>